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Commit 571e7b85 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'sh_eth-R8A77980-GEther-support' 



Sergei Shtylyov says:

====================
Add Renesas R8A77980 GEther support

Here's a set of 3 patches against DaveM's 'net-next.git' repo. They (gradually)
add R8A77980 GEther support to the 'sh_eth' driver, starting with couple new
register bits/values introduced with this chip, and ending with adding a new
'struct sh_eth_cpu_data' instance connected to the new DT "compatible" prop
value...
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 62c8a069 3eb9c2ad

Documentation/devicetree/bindings/net/sh_eth.txt

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ Required properties: 
	      "renesas,ether-r8a7791"  if the device is a part of R8A7791 SoC.

	      "renesas,ether-r8a7793"  if the device is a part of R8A7793 SoC.

	      "renesas,ether-r8a7794"  if the device is a part of R8A7794 SoC.

	      "renesas,gether-r8a77980" if the device is a part of R8A77980 SoC.

	      "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.

	      "renesas,rcar-gen1-ether" for a generic R-Car Gen1 device.

	      "renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1

drivers/net/ethernet/renesas/sh_eth.c

+51 −0
Original line number Diff line number Diff line
@@ -466,6 +466,9 @@ static void sh_eth_select_mii(struct net_device *ndev) 
	u32 value;



	switch (mdp->phy_interface) {

	case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:

		value = 0x3;

		break;

	case PHY_INTERFACE_MODE_GMII:

		value = 0x2;

		break;
@@ -750,6 +753,49 @@ static struct sh_eth_cpu_data rcar_gen2_data = { 
	.rmiimode	= 1,

	.magic		= 1,

};



/* R8A77980 */

static struct sh_eth_cpu_data r8a77980_data = {

	.soft_reset	= sh_eth_soft_reset_gether,



	.set_duplex	= sh_eth_set_duplex,

	.set_rate	= sh_eth_set_rate_gether,



	.register_type  = SH_ETH_REG_GIGABIT,



	.edtrr_trns	= EDTRR_TRNS_GETHER,

	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,

	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |

			  ECSIPR_MPDIP,

	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |

			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |

			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |

			  EESIPR_RMAFIP | EESIPR_RRFIP |

			  EESIPR_RTLFIP | EESIPR_RTSFIP |

			  EESIPR_PREIP | EESIPR_CERFIP,



	.tx_check       = EESR_FTC | EESR_CD | EESR_RTO,

	.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

			  EESR_RFE | EESR_RDE | EESR_RFRMER |

			  EESR_TFE | EESR_TDE | EESR_ECI,

	.fdr_value	= 0x0000070f,



	.apr		= 1,

	.mpr		= 1,

	.tpauser	= 1,

	.bculr		= 1,

	.hw_swap	= 1,

	.nbst		= 1,

	.rpadir		= 1,

	.rpadir_value   = 2 << 16,

	.no_trimd	= 1,

	.no_ade		= 1,

	.xdfar_rw	= 1,

	.hw_checksum	= 1,

	.select_mii	= 1,

	.magic		= 1,

	.cexcr		= 1,

};

#endif /* CONFIG_OF */



static void sh_eth_set_rate_sh7724(struct net_device *ndev)
@@ -1431,6 +1477,10 @@ static int sh_eth_dev_init(struct net_device *ndev) 


	sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);



	/* DMA transfer burst mode */

	if (mdp->cd->nbst)

		sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);



	if (mdp->cd->bculr)

		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */
@@ -3127,6 +3177,7 @@ static const struct of_device_id sh_eth_match_table[] = { 
	{ .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },

	{ .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },

	{ .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },

	{ .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },

	{ .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },

	{ .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },

	{ .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },

drivers/net/ethernet/renesas/sh_eth.h

+2 −0
Original line number Diff line number Diff line
@@ -184,6 +184,7 @@ enum GECMR_BIT { 


/* EDMR */

enum DMAC_M_BIT {

	EDMR_NBST = 0x80,

	EDMR_EL = 0x40, /* Litte endian */

	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,

	EDMR_SRST_GETHER = 0x03,
@@ -505,6 +506,7 @@ struct sh_eth_cpu_data { 
	unsigned bculr:1;	/* EtherC have BCULR */

	unsigned tsu:1;		/* EtherC have TSU */

	unsigned hw_swap:1;	/* E-DMAC have DE bit in EDMR */

	unsigned nbst:1;	/* E-DMAC has NBST bit in EDMR */

	unsigned rpadir:1;	/* E-DMAC have RPADIR */

	unsigned no_trimd:1;	/* E-DMAC DO NOT have TRIMD */

	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */