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Commit 56a64733 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: math-emu: Switch to using the MIPS rounding modes. 



Previously math-emu was using the IEEE-754 constants internally.  These
were differing by having the constants for rounding to +/- infinity
switched, so a conversion was necessary.  This would be entirely
avoidable if the MIPS constants were used throughout, so get rid of
the bloat.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent aef3fb76

arch/mips/math-emu/cp1emu.c

+7 −28
Original line number Diff line number Diff line
@@ -67,21 +67,6 @@ static int fpux_emu(struct pt_regs *, 
/* Determine rounding mode from the RM bits of the FCSR */

#define modeindex(v) ((v) & FPU_CSR_RM)



/* Convert MIPS rounding mode (0..3) to IEEE library modes. */

static const unsigned char ieee_rm[4] = {

	[FPU_CSR_RN] = IEEE754_RN,

	[FPU_CSR_RZ] = IEEE754_RZ,

	[FPU_CSR_RU] = IEEE754_RU,

	[FPU_CSR_RD] = IEEE754_RD,

};

/* Convert IEEE library modes to MIPS rounding mode (0..3). */

static const unsigned char mips_rm[4] = {

	[IEEE754_RN] = FPU_CSR_RN,

	[IEEE754_RZ] = FPU_CSR_RZ,

	[IEEE754_RD] = FPU_CSR_RD,

	[IEEE754_RU] = FPU_CSR_RU,

};



/* convert condition code register number to csr bit */

static const unsigned int fpucondbit[8] = {

	FPU_CSR_COND0,
@@ -907,8 +892,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			/* cop control register rd -> gpr[rt] */

			if (MIPSInst_RD(ir) == FPCREG_CSR) {

				value = ctx->fcr31;

				value = (value & ~FPU_CSR_RM) |

					mips_rm[modeindex(value)];

				value = (value & ~FPU_CSR_RM) | modeindex(value);

				pr_debug("%p gpr[%d]<-csr=%08x\n",

					 (void *) (xcp->cp0_epc),

					 MIPSInst_RT(ir), value);
@@ -939,9 +923,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
				 * Don't write reserved bits,

				 * and convert to ieee library modes

				 */

				ctx->fcr31 = (value &

						~(FPU_CSR_RSVD | FPU_CSR_RM)) |

						ieee_rm[modeindex(value)];

				ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |

					     modeindex(value);

			}

			if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {

				return SIGFPE;
@@ -1515,7 +1498,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 


			oldrm = ieee754_csr.rm;

			SPFROMREG(fs, MIPSInst_FS(ir));

			ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];

			ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));

			rv.w = ieee754sp_tint(fs);

			ieee754_csr.rm = oldrm;

			rfmt = w_fmt;
@@ -1539,7 +1522,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 


			oldrm = ieee754_csr.rm;

			SPFROMREG(fs, MIPSInst_FS(ir));

			ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];

			ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));

			rv.l = ieee754sp_tlong(fs);

			ieee754_csr.rm = oldrm;

			rfmt = l_fmt;
@@ -1692,7 +1675,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 


			oldrm = ieee754_csr.rm;

			DPFROMREG(fs, MIPSInst_FS(ir));

			ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];

			ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));

			rv.w = ieee754dp_tint(fs);

			ieee754_csr.rm = oldrm;

			rfmt = w_fmt;
@@ -1716,7 +1699,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 


			oldrm = ieee754_csr.rm;

			DPFROMREG(fs, MIPSInst_FS(ir));

			ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];

			ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));

			rv.l = ieee754dp_tlong(fs);

			ieee754_csr.rm = oldrm;

			rfmt = l_fmt;
@@ -1926,11 +1909,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
			 * ieee754_csr.	 But ieee754_csr.rm is ieee

			 * library modes. (not mips rounding mode)

			 */

			/* convert to ieee library modes */

			ieee754_csr.rm = ieee_rm[ieee754_csr.rm];

			sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);

			/* revert to mips rounding mode */

			ieee754_csr.rm = mips_rm[ieee754_csr.rm];

		}



		if (has_fpu)

arch/mips/math-emu/dp_add.c

+2 −2
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y) 
		if (xs == ys)

			return x;

		else

			return ieee754dp_zero(ieee754_csr.rm == IEEE754_RD);

			return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);



	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):

	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
@@ -168,7 +168,7 @@ union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y) 
			xs = ys;

		}

		if (xm == 0)

			return ieee754dp_zero(ieee754_csr.rm == IEEE754_RD);

			return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);



		/*

		 * Normalize to rounding precision.

arch/mips/math-emu/dp_sqrt.c

+4 −4
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x) 
	oldcsr = ieee754_csr;

	ieee754_csr.mx &= ~IEEE754_INEXACT;

	ieee754_csr.sx &= ~IEEE754_INEXACT;

	ieee754_csr.rm = IEEE754_RN;

	ieee754_csr.rm = FPU_CSR_RN;



	/* adjust exponent to prevent overflow */

	scalx = 0;
@@ -122,7 +122,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x) 
	/* twiddle last bit to force y correctly rounded */



	/* set RZ, clear INEX flag */

	ieee754_csr.rm = IEEE754_RZ;

	ieee754_csr.rm = FPU_CSR_RZ;

	ieee754_csr.sx &= ~IEEE754_INEXACT;



	/* t=x/y; ...chopped quotient, possibly inexact */
@@ -139,10 +139,10 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x) 
		oldcsr.sx |= IEEE754_INEXACT;



		switch (oldcsr.rm) {

		case IEEE754_RU:

		case FPU_CSR_RU:

			y.bits += 1;

			/* drop through */

		case IEEE754_RN:

		case FPU_CSR_RN:

			t.bits += 1;

			break;

		}

arch/mips/math-emu/dp_sub.c

+2 −2
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y) 
		if (xs != ys)

			return x;

		else

			return ieee754dp_zero(ieee754_csr.rm == IEEE754_RD);

			return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);



	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):

	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
@@ -171,7 +171,7 @@ union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y) 
			xs = ys;

		}

		if (xm == 0) {

			if (ieee754_csr.rm == IEEE754_RD)

			if (ieee754_csr.rm == FPU_CSR_RD)

				return ieee754dp_zero(1);	/* round negative inf. => sign = -1 */

			else

				return ieee754dp_zero(0);	/* other round modes   => sign = 1 */

arch/mips/math-emu/dp_tint.c

+4 −4
Original line number Diff line number Diff line
@@ -74,17 +74,17 @@ int ieee754dp_tint(union ieee754dp x) 
		   to be zero */

		odd = (xm & 0x1) != 0x0;

		switch (ieee754_csr.rm) {

		case IEEE754_RN:

		case FPU_CSR_RN:

			if (round && (sticky || odd))

				xm++;

			break;

		case IEEE754_RZ:

		case FPU_CSR_RZ:

			break;

		case IEEE754_RU:	/* toward +Infinity */

		case FPU_CSR_RU:	/* toward +Infinity */

			if ((round || sticky) && !xs)

				xm++;

			break;

		case IEEE754_RD:	/* toward -Infinity */

		case FPU_CSR_RD:	/* toward -Infinity */

			if ((round || sticky) && xs)

				xm++;

			break;