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Commit 5686b06c authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
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arm64: lockref: add support for lockless lockrefs using cmpxchg 



Our spinlocks are only 32-bit (2x16-bit tickets) and our cmpxchg can
deal with 8-bytes (as one would hope!).

This patch wires up the cmpxchg-based lockless lockref implementation
for arm64.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 52ea2a56

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line 
config ARM64

	def_bool y

	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE

	select ARCH_USE_CMPXCHG_LOCKREF

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION

	select ARCH_WANT_FRAME_POINTERS

arch/arm64/include/asm/spinlock.h

+6 −2
Original line number Diff line number Diff line
@@ -92,10 +92,14 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock) 
	: "memory");

}



static inline int arch_spin_value_unlocked(arch_spinlock_t lock)

{

	return lock.owner == lock.next;

}



static inline int arch_spin_is_locked(arch_spinlock_t *lock)

{

	arch_spinlock_t lockval = ACCESS_ONCE(*lock);

	return lockval.owner != lockval.next;

	return !arch_spin_value_unlocked(ACCESS_ONCE(*lock));

}



static inline int arch_spin_is_contended(arch_spinlock_t *lock)