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Commit 550e2d92 authored by Dave Airlie's avatar Dave Airlie
Browse files

drm/radeon/kms: restore surface registers on resume. 



On resume on my rv530 laptop surface cntl was left disabled, so
wierd stuff would happen with rendering to a tiled front buffer.

This checks if the surface regs are assigned to bos and reprograms
the surface registers on resume using the same path that clears
them all on init.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 779720a3

drivers/gpu/drm/radeon/r100.c

+2 −0
Original line number Diff line number Diff line
@@ -3299,6 +3299,8 @@ int r100_resume(struct radeon_device *rdev) 
	radeon_combios_asic_init(rdev->ddev);

	/* Resume clock after posting */

	r100_clock_startup(rdev);

	/* Initialize surface registers */

	radeon_surface_init(rdev);

	return r100_startup(rdev);

}

drivers/gpu/drm/radeon/r300.c

+2 −0
Original line number Diff line number Diff line
@@ -1250,6 +1250,8 @@ int r300_resume(struct radeon_device *rdev) 
	radeon_combios_asic_init(rdev->ddev);

	/* Resume clock after posting */

	r300_clock_startup(rdev);

	/* Initialize surface registers */

	radeon_surface_init(rdev);

	return r300_startup(rdev);

}

drivers/gpu/drm/radeon/r420.c

+2 −1
Original line number Diff line number Diff line
@@ -231,7 +231,8 @@ int r420_resume(struct radeon_device *rdev) 
	}

	/* Resume clock after posting */

	r420_clock_resume(rdev);



	/* Initialize surface registers */

	radeon_surface_init(rdev);

	return r420_startup(rdev);

}

drivers/gpu/drm/radeon/r520.c

+2 −0
Original line number Diff line number Diff line
@@ -220,6 +220,8 @@ int r520_resume(struct radeon_device *rdev) 
	atom_asic_init(rdev->mode_info.atom_context);

	/* Resume clock after posting */

	rv515_clock_startup(rdev);

	/* Initialize surface registers */

	radeon_surface_init(rdev);

	return r520_startup(rdev);

}

drivers/gpu/drm/radeon/radeon_device.c

+5 −4
Original line number Diff line number Diff line
@@ -44,10 +44,11 @@ void radeon_surface_init(struct radeon_device *rdev) 
	if (rdev->family < CHIP_R600) {

		int i;



		for (i = 0; i < 8; i++) {

			WREG32(RADEON_SURFACE0_INFO +

			       i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),

			       0);

		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {

			if (rdev->surface_regs[i].bo)

				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);

			else

				radeon_clear_surface_reg(rdev, i);

		}

		/* enable surfaces */

		WREG32(RADEON_SURFACE_CNTL, 0);