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Commit 54ec12af authored by Chris Wilson's avatar Chris Wilson
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drm/i915: Skip force-wake for uncached mmio flush of GGTT writes 



The trick of using an uncached mmio read to ensure that the GGTT writes
are flushed does not require us to do the forcewake dance, so avoid it
in the hope of reducing the frequency that we do keep the device forced
awake.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170318104257.694-1-chris@chris-wilson.co.uk


Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
parent c9203e82

drivers/gpu/drm/i915/i915_gem.c

+5 −2
Original line number Diff line number Diff line
@@ -3307,8 +3307,11 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) 
	 * system agents we cannot reproduce this behaviour).

	 */

	wmb();

	if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))

		POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));

	if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {

		spin_lock_irq(&dev_priv->uncore.lock);

		POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));

		spin_unlock_irq(&dev_priv->uncore.lock);

	}



	intel_fb_obj_flush(obj, write_origin(obj, I915_GEM_DOMAIN_GTT));