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Commit 54b3d182 authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'v3.19-rockchip-clk1' of... 

Merge tag 'v3.19-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next-rockchip

- fixes for clock ordering/rate issues
- do not keep all clocks enabled anymore
- allow special pll rates for special cases
parents 6f8a444a 29e94468

drivers/clk/rockchip/clk-rk3188.c

+21 −21
Original line number Diff line number Diff line
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	GATE(0, "hclk_vdpu", "aclk_vdpu", 0,

			RK2928_CLKGATE_CON(3), 12, GFLAGS),



	GATE(0, "gpll_ddr", "gpll", 0,

	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(1), 7, GFLAGS),

	COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,

	COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,

			RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,

			RK2928_CLKGATE_CON(0), 2, GFLAGS),
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(0), 6, GFLAGS),

	GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,

			RK2928_CLKGATE_CON(0), 5, GFLAGS),

	GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,

	GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(0), 4, GFLAGS),



	COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,

	COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,

			RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,

			RK2928_CLKGATE_CON(3), 0, GFLAGS),

	COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	 * the 480m are generated inside the usb block from these clocks,

	 * but they are also a source for the hsicphy clock.

	 */

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,

	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(1), 5, GFLAGS),

	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,

	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(1), 6, GFLAGS),



	COMPOSITE(0, "mac_src", mux_mac_p, 0,
@@ -320,9 +320,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,

			RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,

			RK2928_CLKGATE_CON(2), 6, GFLAGS),

	COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",

	COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0,

			RK2928_CLKSEL_CON(23), 0,

			RK2928_CLKGATE_CON(2), 7, 0, GFLAGS),

			RK2928_CLKGATE_CON(2), 7, GFLAGS),

	MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,

			RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
@@ -399,8 +399,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 


	/* aclk_cpu gates */

	GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),

	GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS),

	GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS),

	GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),

	GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),



	/* hclk_cpu gates */

	GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
@@ -416,8 +416,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),



	/* hclk_peri gates */

	GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS),

	GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS),

	GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),

	GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),

	GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),

	GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),

	GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
@@ -457,18 +457,18 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),

	GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),

	GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),

	GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS),

	GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS),

	GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),

	GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),



	/* aclk_peri */

	GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),

	GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),

	GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS),

	GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS),

	GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS),

	GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),

	GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),

	GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),



	/* pclk_peri gates */

	GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS),

	GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),

	GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),

	GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),

	GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
@@ -511,7 +511,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { 
							    | CLK_DIVIDER_READ_ONLY,

			RK2928_CLKGATE_CON(4), 9, GFLAGS),



	GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0,

	GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(9), 4, GFLAGS),



	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
@@ -618,7 +618,7 @@ PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1", 
				    "gpll", "cpll" };



static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {

	COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,

	COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,

			RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,

			div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
@@ -633,7 +633,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { 
			RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,

			RK2928_CLKGATE_CON(4), 9, GFLAGS),



	GATE(CORE_L2C, "core_l2c", "armclk", 0,

	GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(9), 4, GFLAGS),



	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,

drivers/clk/rockchip/clk-rk3288.c

+139 −77

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/rockchip/clk.c

+0 −9
Original line number Diff line number Diff line
@@ -246,9 +246,6 @@ void __init rockchip_clk_register_branches( 
					list->div_flags, &clk_lock);

			break;

		case branch_fraction_divider:

			/* keep all gates untouched for now */

			flags |= CLK_IGNORE_UNUSED;



			clk = rockchip_clk_register_frac_branch(list->name,

				list->parent_names, list->num_parents,

				reg_base, list->muxdiv_offset, list->div_flags,
@@ -258,18 +255,12 @@ void __init rockchip_clk_register_branches( 
		case branch_gate:

			flags |= CLK_SET_RATE_PARENT;



			/* keep all gates untouched for now */

			flags |= CLK_IGNORE_UNUSED;



			clk = clk_register_gate(NULL, list->name,

				list->parent_names[0], flags,

				reg_base + list->gate_offset,

				list->gate_shift, list->gate_flags, &clk_lock);

			break;

		case branch_composite:

			/* keep all gates untouched for now */

			flags |= CLK_IGNORE_UNUSED;



			clk = rockchip_clk_register_branch(list->name,

				list->parent_names, list->num_parents,

				reg_base, list->muxdiv_offset, list->mux_shift,

drivers/clk/rockchip/clk.h

+9 −0
Original line number Diff line number Diff line
@@ -62,6 +62,15 @@ enum rockchip_pll_type { 
	.bwadj = (_nf >> 1),			\

}



#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw)	\

{								\

	.rate	= _rate##U,					\

	.nr = _nr,						\

	.nf = _nf,						\

	.no = _no,						\

	.bwadj = _bw,						\

}



struct rockchip_pll_rate_table {

	unsigned long rate;

	unsigned int nr;