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Commit 5430a3ff authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: fix UVD/VCE fence handling 



We need to return the sequence number to userspace
even when we don't use user fences.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5ceb54c6

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -414,8 +414,6 @@ struct amdgpu_user_fence { 
	struct amdgpu_bo 	*bo;

	struct amdgpu_bo 	*bo;

	/* write-back address offset to bo start */

	/* write-back address offset to bo start */

	uint32_t                offset;

	uint32_t                offset;

	/* resulting sequence number */

	uint64_t                sequence;

};

};





int amdgpu_fence_driver_init(struct amdgpu_device *adev);

int amdgpu_fence_driver_init(struct amdgpu_device *adev);
@@ -847,6 +845,8 @@ struct amdgpu_ib { 
	uint32_t			gws_base, gws_size;

	uint32_t			gws_base, gws_size;

	uint32_t			oa_base, oa_size;

	uint32_t			oa_base, oa_size;

	uint32_t			flags;

	uint32_t			flags;

	/* resulting sequence number */

	uint64_t			sequence;

};

};





enum amdgpu_ring_type {

enum amdgpu_ring_type {

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -794,7 +794,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
		goto out;

		goto out;

	}

	}





	cs->out.handle = parser.uf.sequence;

	cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;

out:

out:

	amdgpu_cs_parser_fini(&parser, r, true);

	amdgpu_cs_parser_fini(&parser, r, true);

	up_read(&adev->exclusive_lock);

	up_read(&adev->exclusive_lock);

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+6 −3
Original line number Original line Diff line number Diff line
@@ -88,6 +88,7 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 
	ib->fence = NULL;

	ib->fence = NULL;

	ib->user = NULL;

	ib->user = NULL;

	ib->vm = vm;

	ib->vm = vm;

	ib->ctx = NULL;

	ib->gds_base = 0;

	ib->gds_base = 0;

	ib->gds_size = 0;

	ib->gds_size = 0;

	ib->gws_base = 0;

	ib->gws_base = 0;
@@ -214,13 +215,15 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 
		return r;

		return r;

	}

	}





	if (ib->ctx)

		ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,

						    &ib->fence->base);



	/* wrap the last IB with fence */

	/* wrap the last IB with fence */

	if (ib->user) {

	if (ib->user) {

		uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);

		uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);

		ib->user->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,

							  &ib->fence->base);

		addr += ib->user->offset;

		addr += ib->user->offset;

		amdgpu_ring_emit_fence(ring, addr, ib->user->sequence,

		amdgpu_ring_emit_fence(ring, addr, ib->sequence,

				       AMDGPU_FENCE_FLAG_64BIT);

				       AMDGPU_FENCE_FLAG_64BIT);

	}

	}