Loading drivers/gpio/gpio-omap.c +25 −22 Original line number Diff line number Diff line Loading @@ -120,10 +120,13 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) void __iomem *reg = bank->base; u32 l = GPIO_BIT(bank, gpio); if (enable) if (enable) { reg += bank->regs->set_dataout; else bank->context.dataout |= l; } else { reg += bank->regs->clr_dataout; bank->context.dataout &= ~l; } __raw_writel(l, reg); } Loading @@ -144,18 +147,18 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) bank->context.dataout = l; } static int _get_gpio_datain(struct gpio_bank *bank, int gpio) static int _get_gpio_datain(struct gpio_bank *bank, int offset) { void __iomem *reg = bank->base + bank->regs->datain; return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; return (__raw_readl(reg) & (1 << offset)) != 0; } static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) static int _get_gpio_dataout(struct gpio_bank *bank, int offset) { void __iomem *reg = bank->base + bank->regs->dataout; return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; return (__raw_readl(reg) & (1 << offset)) != 0; } static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) Loading Loading @@ -245,7 +248,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, } static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, int trigger) unsigned trigger) { void __iomem *base = bank->base; u32 gpio_bit = 1 << gpio; Loading Loading @@ -327,7 +330,8 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} #endif static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, unsigned trigger) { void __iomem *reg = bank->base; void __iomem *base = bank->base; Loading Loading @@ -447,6 +451,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) if (bank->regs->set_irqenable) { reg += bank->regs->set_irqenable; l = gpio_mask; bank->context.irqenable1 |= gpio_mask; } else { reg += bank->regs->irqenable; l = __raw_readl(reg); Loading @@ -454,10 +459,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) l &= ~gpio_mask; else l |= gpio_mask; bank->context.irqenable1 = l; } __raw_writel(l, reg); bank->context.irqenable1 = l; } static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) Loading @@ -468,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) if (bank->regs->clr_irqenable) { reg += bank->regs->clr_irqenable; l = gpio_mask; bank->context.irqenable1 &= ~gpio_mask; } else { reg += bank->regs->irqenable; l = __raw_readl(reg); Loading @@ -475,15 +481,18 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) l |= gpio_mask; else l &= ~gpio_mask; bank->context.irqenable1 = l; } __raw_writel(l, reg); bank->context.irqenable1 = l; } static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) { if (enable) _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); else _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); } /* Loading Loading @@ -511,6 +520,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) else bank->suspend_wakeup &= ~gpio_bit; __raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en); spin_unlock_irqrestore(&bank->lock, flags); return 0; Loading Loading @@ -855,19 +865,15 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) static int gpio_get(struct gpio_chip *chip, unsigned offset) { struct gpio_bank *bank; void __iomem *reg; int gpio; u32 mask; gpio = chip->base + offset; bank = container_of(chip, struct gpio_bank, chip); reg = bank->base; mask = GPIO_BIT(bank, gpio); mask = (1 << offset); if (gpio_is_input(bank, mask)) return _get_gpio_datain(bank, gpio); return _get_gpio_datain(bank, offset); else return _get_gpio_dataout(bank, gpio); return _get_gpio_dataout(bank, offset); } static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) Loading Loading @@ -1239,9 +1245,6 @@ static int omap_gpio_runtime_suspend(struct device *dev) * non-wakeup GPIOs. Otherwise spurious IRQs will be * generated. See OMAP2420 Errata item 1.101. */ if (!(bank->enabled_non_wakeup_gpios)) goto update_gpio_context_count; bank->saved_datain = __raw_readl(bank->base + bank->regs->datain); l1 = __raw_readl(bank->base + bank->regs->fallingdetect); Loading Loading @@ -1290,7 +1293,7 @@ static int omap_gpio_runtime_resume(struct device *dev) __raw_writel(bank->context.risingdetect, bank->base + bank->regs->risingdetect); if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) { if (!bank->workaround_enabled) { spin_unlock_irqrestore(&bank->lock, flags); return 0; } Loading Loading
drivers/gpio/gpio-omap.c +25 −22 Original line number Diff line number Diff line Loading @@ -120,10 +120,13 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) void __iomem *reg = bank->base; u32 l = GPIO_BIT(bank, gpio); if (enable) if (enable) { reg += bank->regs->set_dataout; else bank->context.dataout |= l; } else { reg += bank->regs->clr_dataout; bank->context.dataout &= ~l; } __raw_writel(l, reg); } Loading @@ -144,18 +147,18 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) bank->context.dataout = l; } static int _get_gpio_datain(struct gpio_bank *bank, int gpio) static int _get_gpio_datain(struct gpio_bank *bank, int offset) { void __iomem *reg = bank->base + bank->regs->datain; return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; return (__raw_readl(reg) & (1 << offset)) != 0; } static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) static int _get_gpio_dataout(struct gpio_bank *bank, int offset) { void __iomem *reg = bank->base + bank->regs->dataout; return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; return (__raw_readl(reg) & (1 << offset)) != 0; } static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) Loading Loading @@ -245,7 +248,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, } static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, int trigger) unsigned trigger) { void __iomem *base = bank->base; u32 gpio_bit = 1 << gpio; Loading Loading @@ -327,7 +330,8 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} #endif static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, unsigned trigger) { void __iomem *reg = bank->base; void __iomem *base = bank->base; Loading Loading @@ -447,6 +451,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) if (bank->regs->set_irqenable) { reg += bank->regs->set_irqenable; l = gpio_mask; bank->context.irqenable1 |= gpio_mask; } else { reg += bank->regs->irqenable; l = __raw_readl(reg); Loading @@ -454,10 +459,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) l &= ~gpio_mask; else l |= gpio_mask; bank->context.irqenable1 = l; } __raw_writel(l, reg); bank->context.irqenable1 = l; } static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) Loading @@ -468,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) if (bank->regs->clr_irqenable) { reg += bank->regs->clr_irqenable; l = gpio_mask; bank->context.irqenable1 &= ~gpio_mask; } else { reg += bank->regs->irqenable; l = __raw_readl(reg); Loading @@ -475,15 +481,18 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) l |= gpio_mask; else l &= ~gpio_mask; bank->context.irqenable1 = l; } __raw_writel(l, reg); bank->context.irqenable1 = l; } static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) { if (enable) _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); else _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); } /* Loading Loading @@ -511,6 +520,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) else bank->suspend_wakeup &= ~gpio_bit; __raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en); spin_unlock_irqrestore(&bank->lock, flags); return 0; Loading Loading @@ -855,19 +865,15 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) static int gpio_get(struct gpio_chip *chip, unsigned offset) { struct gpio_bank *bank; void __iomem *reg; int gpio; u32 mask; gpio = chip->base + offset; bank = container_of(chip, struct gpio_bank, chip); reg = bank->base; mask = GPIO_BIT(bank, gpio); mask = (1 << offset); if (gpio_is_input(bank, mask)) return _get_gpio_datain(bank, gpio); return _get_gpio_datain(bank, offset); else return _get_gpio_dataout(bank, gpio); return _get_gpio_dataout(bank, offset); } static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) Loading Loading @@ -1239,9 +1245,6 @@ static int omap_gpio_runtime_suspend(struct device *dev) * non-wakeup GPIOs. Otherwise spurious IRQs will be * generated. See OMAP2420 Errata item 1.101. */ if (!(bank->enabled_non_wakeup_gpios)) goto update_gpio_context_count; bank->saved_datain = __raw_readl(bank->base + bank->regs->datain); l1 = __raw_readl(bank->base + bank->regs->fallingdetect); Loading Loading @@ -1290,7 +1293,7 @@ static int omap_gpio_runtime_resume(struct device *dev) __raw_writel(bank->context.risingdetect, bank->base + bank->regs->risingdetect); if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) { if (!bank->workaround_enabled) { spin_unlock_irqrestore(&bank->lock, flags); return 0; } Loading