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Commit 541ac155 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sun5i: Add DRAM gates 



The DRAM gates control whether the image / display devices on the SoC have
access to the DRAM clock or not.

Enable it.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 15bd920f

arch/arm/boot/dts/sun5i-a13.dtsi

+22 −1
Original line number Diff line number Diff line
@@ -61,7 +61,8 @@ 
			compatible = "allwinner,simple-framebuffer",

				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0";

			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;

			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,

				 <&dram_gates 26>;

			status = "disabled";

		};

	};
@@ -149,6 +150,26 @@ 
					     "apb1_i2c2", "apb1_uart1",

					     "apb1_uart3";

		};



		dram_gates: clk@01c20100 {

			#clock-cells = <1>;

			compatible = "allwinner,sun5i-a13-dram-gates-clk",

				     "allwinner,sun4i-a10-gates-clk";

			reg = <0x01c20100 0x4>;

			clocks = <&pll5 0>;

			clock-indices = <0>,

					<1>,

					<25>,

					<26>,

					<29>,

					<31>;

			clock-output-names = "dram_ve",

					     "dram_csi",

					     "dram_de_fe",

					     "dram_de_be",

					     "dram_ace",

					     "dram_iep";

		};

	};



	soc@01c00000 {

arch/arm/boot/dts/sun5i-r8.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ 
				     "simple-framebuffer";

			allwinner,pipeline = "de_be0-lcd0-tve0";

			clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,

				 <&ahb_gates 44>;

				 <&ahb_gates 44>, <&dram_gates 26>;

			status = "disabled";

		};

	};