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Commit 53a7915c authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Add FIFO underrun tracepoints 



Add tracepoints for display FIFO underruns. Makes it more convenient to
correlate the underruns with other display tracepoints.

v2: s/i915/intel/ in the tracepoint name

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170302171508.1666-19-ville.syrjala@linux.intel.com
parent 1489bba8

drivers/gpu/drm/i915/i915_trace.h

+43 −0
Original line number Diff line number Diff line
@@ -16,6 +16,49 @@ 


/* watermark/fifo updates */



TRACE_EVENT(intel_cpu_fifo_underrun,

	    TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pipe),

	    TP_ARGS(dev_priv, pipe),



	    TP_STRUCT__entry(

			     __field(enum pipe, pipe)

			     __field(u32, frame)

			     __field(u32, scanline)

			     ),



	    TP_fast_assign(

			   __entry->pipe = pipe;

			   __entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe);

			   __entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe));

			   ),



	    TP_printk("pipe %c, frame=%u, scanline=%u",

		      pipe_name(__entry->pipe),

		      __entry->frame, __entry->scanline)

);



TRACE_EVENT(intel_pch_fifo_underrun,

	    TP_PROTO(struct drm_i915_private *dev_priv, enum transcoder pch_transcoder),

	    TP_ARGS(dev_priv, pch_transcoder),



	    TP_STRUCT__entry(

			     __field(enum pipe, pipe)

			     __field(u32, frame)

			     __field(u32, scanline)

			     ),



	    TP_fast_assign(

			   enum pipe pipe = (enum pipe)pch_transcoder;

			   __entry->pipe = pipe;

			   __entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe);

			   __entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe));

			   ),



	    TP_printk("pch transcoder %c, frame=%u, scanline=%u",

		      pipe_name(__entry->pipe),

		      __entry->frame, __entry->scanline)

);



TRACE_EVENT(intel_memory_cxsr,

	    TP_PROTO(struct drm_i915_private *dev_priv, bool old, bool new),

	    TP_ARGS(dev_priv, old, new),

drivers/gpu/drm/i915/intel_fifo_underrun.c

+9 −2
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) 
	I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);

	POSTING_READ(reg);



	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);

	DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));

}
@@ -147,6 +148,7 @@ static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc) 
	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

	POSTING_READ(GEN7_ERR_INT);



	trace_intel_cpu_fifo_underrun(dev_priv, pipe);

	DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));

}
@@ -212,6 +214,7 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) 
	I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

	POSTING_READ(SERR_INT);



	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);

	DRM_ERROR("pch fifo underrun on pch transcoder %s\n",

		  transcoder_name(pch_transcoder));

}
@@ -368,9 +371,11 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 
	    crtc->cpu_fifo_underrun_disabled)

		return;



	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false))

	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {

		trace_intel_cpu_fifo_underrun(dev_priv, pipe);

		DRM_ERROR("CPU pipe %c FIFO underrun\n",

			  pipe_name(pipe));

	}



	intel_fbc_handle_fifo_underrun_irq(dev_priv);

}
@@ -388,10 +393,12 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 
					 enum transcoder pch_transcoder)

{

	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,

						  false))

						  false)) {

		trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);

		DRM_ERROR("PCH transcoder %s FIFO underrun\n",

			  transcoder_name(pch_transcoder));

	}

}



/**

 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately