Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 51b5df88 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-flow-control' 



Vince Bridgers says:

====================
stmmac: Correct flow control configuration

This series of patches corrects flow control configuration for the Synopsys
GMAC driver.

Flow control is configured based on a configurable receive fifo size. If
less than 4Kbytes flow control is left disabled and a warning is presented. If
a receive fifo size is not specified, flow control is left disabled to
maintain current behavior. Unicast pause detection was disabled, but is now
enabled. The pause time was modified to be maximum time per a XON/XOFF
flow control mode of operation.

This patch was tested on an Altera Cyclone 5 and an Altera Arria 10 devkit,
and verified that flow control operates as expected when enabled.

Please consider this series for inclusion so that flow control will
function as expected for the Synopsys GMAC controller.
====================

Acked-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e743471f f88203a2

Documentation/devicetree/bindings/net/ethernet.txt

+6 −0
Original line number Diff line number Diff line
@@ -19,6 +19,12 @@ The following properties are common to the Ethernet controllers: 
- phy: the same as "phy-handle" property, not recommended for new bindings.

- phy-device: the same as "phy-handle" property, not recommended for new

  bindings.

- rx-fifo-depth: the size of the controller's receive fifo in bytes. This

  is used for components that can have configurable receive fifo sizes,

  and is useful for determining certain configuration settings such as

  flow control thresholds.

- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This

  is used for components that can have configurable fifo sizes.



Child nodes of the Ethernet controller are typically the individual PHY devices

connected via the MDIO bus (sometimes the MDIO bus controller is separate).

Documentation/devicetree/bindings/net/stmmac.txt

+4 −0
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ Optional properties: 
  If not passed then the system clock will be used and this is fine on some

  platforms.

- snps,burst_len: The AXI burst lenth value of the AXI BUS MODE register.

- tx-fifo-depth: See ethernet.txt file in the same directory

- rx-fifo-depth: See ethernet.txt file in the same directory



Examples:
@@ -59,6 +61,8 @@ Examples: 
		phy-mode = "gmii";

		snps,multicast-filter-bins = <256>;

		snps,perfect-filter-entries = <128>;

		rx-fifo-depth = <16384>;

		tx-fifo-depth = <16384>;

		clocks = <&clock>;

		clock-names = "stmmaceth";

	};

drivers/net/ethernet/stmicro/stmmac/common.h

+3 −2
Original line number Diff line number Diff line
@@ -150,7 +150,7 @@ struct stmmac_extra_stats { 
#define	MAC_CSR_H_FRQ_MASK	0x20



#define HASH_TABLE_SIZE 64

#define PAUSE_TIME 0x200

#define PAUSE_TIME 0xffff



/* Flow Control defines */

#define FLOW_OFF	0
@@ -357,7 +357,8 @@ struct stmmac_dma_ops { 
	void (*dump_regs) (void __iomem *ioaddr);

	/* Set tx/rx threshold in the csr6 register

	 * An invalid value enables the store-and-forward mode */

	void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);

	void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,

			 int rxfifosz);

	/* To track extra statistic (if supported) */

	void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,

				   void __iomem *ioaddr);

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+51 −0
Original line number Diff line number Diff line
@@ -172,6 +172,7 @@ enum inter_frame_gap { 
/* GMAC FLOW CTRL defines */

#define GMAC_FLOW_CTRL_PT_MASK	0xffff0000	/* Pause Time Mask */

#define GMAC_FLOW_CTRL_PT_SHIFT	16

#define GMAC_FLOW_CTRL_UP	0x00000008	/* Unicast pause frame enable */

#define GMAC_FLOW_CTRL_RFE	0x00000004	/* Rx Flow Control Enable */

#define GMAC_FLOW_CTRL_TFE	0x00000002	/* Tx Flow Control Enable */

#define GMAC_FLOW_CTRL_FCB_BPA	0x00000001	/* Flow Control Busy ... */
@@ -246,6 +247,56 @@ enum ttc_control { 
#define DMA_CONTROL_FEF		0x00000080

#define DMA_CONTROL_FUF		0x00000040



/* Receive flow control activation field

 * RFA field in DMA control register, bits 23,10:9

 */

#define DMA_CONTROL_RFA_MASK	0x00800600



/* Receive flow control deactivation field

 * RFD field in DMA control register, bits 22,12:11

 */

#define DMA_CONTROL_RFD_MASK	0x00401800



/* RFD and RFA fields are encoded as follows

 *

 *   Bit Field

 *   0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)

 *   0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)

 *   0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)

 *   0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)

 *   1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)

 *   1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)

 *   1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)

 *   1,11 - Reserved

 *

 * RFD should always be > RFA for a given FIFO size. RFD == RFA may work,

 * but packet throughput performance may not be as expected.

 *

 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame

 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause

 * Description).

 *

 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),

 * is set to 0. This allows pause frames with a quanta of 0 to be sent

 * as an XOFF message to the link peer.

 */



#define RFA_FULL_MINUS_1K	0x00000000

#define RFA_FULL_MINUS_2K	0x00000200

#define RFA_FULL_MINUS_3K	0x00000400

#define RFA_FULL_MINUS_4K	0x00000600

#define RFA_FULL_MINUS_5K	0x00800000

#define RFA_FULL_MINUS_6K	0x00800200

#define RFA_FULL_MINUS_7K	0x00800400



#define RFD_FULL_MINUS_1K	0x00000000

#define RFD_FULL_MINUS_2K	0x00000800

#define RFD_FULL_MINUS_3K	0x00001000

#define RFD_FULL_MINUS_4K	0x00001800

#define RFD_FULL_MINUS_5K	0x00400000

#define RFD_FULL_MINUS_6K	0x00400800

#define RFD_FULL_MINUS_7K	0x00401000



enum rtc_control {

	DMA_CONTROL_RTC_64 = 0x00000000,

	DMA_CONTROL_RTC_32 = 0x00000008,

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+4 −1
Original line number Diff line number Diff line
@@ -201,7 +201,10 @@ static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, 
				unsigned int fc, unsigned int pause_time)

{

	void __iomem *ioaddr = hw->pcsr;

	unsigned int flow = 0;

	/* Set flow such that DZPQ in Mac Register 6 is 0,

	 * and unicast pause detect is enabled.

	 */

	unsigned int flow = GMAC_FLOW_CTRL_UP;



	pr_debug("GMAC Flow-Control:\n");

	if (fc & FLOW_RX) {