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Commit 51933b10 authored by Harunobu Kurokawa's avatar Harunobu Kurokawa Committed by Simon Horman
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arm64: dts: renesas: r8a7796: Add PCIe device nodes 



This patch adds PCIe{0,1} device nodes for R8A7796 SoC.

Signed-off-by: default avatarHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 7085f5d9

arch/arm64/boot/dts/renesas/r8a7796.dtsi

+47 −3
Original line number Diff line number Diff line 
/*

 * Device Tree Source for the r8a7796 SoC

 *

 * Copyright (C) 2016 Renesas Electronics Corp.

 * Copyright (C) 2016-2017 Renesas Electronics Corp.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any
@@ -2108,13 +2108,57 @@ 
		};



		pciec0: pcie@fe000000 {

			compatible = "renesas,pcie-r8a7796",

				     "renesas,pcie-rcar-gen3";

			reg = <0 0xfe000000 0 0x80000>;

			/* placeholder */

			#address-cells = <3>;

			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			device_type = "pci";

			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000

				0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000

				0x02000000 0 0x30000000 0 0x30000000 0 0x08000000

				0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;

			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			status = "disabled";

		};



		pciec1: pcie@ee800000 {

			compatible = "renesas,pcie-r8a7796",

				     "renesas,pcie-rcar-gen3";

			reg = <0 0xee800000 0 0x80000>;

			/* placeholder */

			#address-cells = <3>;

			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			device_type = "pci";

			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000

				0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000

				0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000

				0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;

			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			status = "disabled";

		};



		imr-lx4@fe860000 {