Commit 51847fb9 authored Apr 07, 2015 by Arun Siluvery Committed by Daniel Vetter Apr 10, 2015

drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor



According to Spec this is a reserved bit for Gen9+ and should not be set.

Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent b833bb61

drivers/gpu/drm/i915/intel_lrc.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -265,6 +265,7 @@ static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,

		desc = GEN8_CTX_VALID;
		desc \|= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
		if (IS_GEN8(ctx_obj->base.dev))
		desc \|= GEN8_CTX_L3LLC_COHERENT;
		desc \|= GEN8_CTX_PRIVILEGE;
		desc \|= lrca;