Merge 4.9-rc3 into tty-next (5131dcd7) · Commits · e / devices / android_kernel_teracube_emerald

CREDITS

+3 −2

Original line number	Diff line number	Diff line
		@@ -1864,10 +1864,11 @@ S: The Netherlands

		N: Martin Kepplinger
		E: martink@posteo.de
		E: martin.kepplinger@theobroma-systems.com
		E: martin.kepplinger@ginzinger.com
		W: http://www.martinkepplinger.com
		D: mma8452 accelerators iio driver
		D: Kernel cleanups
		D: pegasus_notetaker input driver
		D: Kernel fixes and cleanups
		S: Garnisonstraße 26
		S: 4020 Linz
		S: Austria

Documentation/device-mapper/dm-raid.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -309,3 +309,4 @@ Version History
		with a reshape in progress.
		1.9.0 Add support for RAID level takeover/reshape/region size
		and set size reduction.
		1.9.1 Fix activation of existing RAID 4/10 mapped devices

Documentation/devicetree/bindings/clock/uniphier-clock.txt

+8 −8

Original line number	Diff line number	Diff line
		@@ -24,7 +24,7 @@ Example:
		reg = <0x61840000 0x4000>;

		clock {
		compatible = "socionext,uniphier-ld20-clock";
		compatible = "socionext,uniphier-ld11-clock";
		#clock-cells = <1>;
		};

		@@ -43,8 +43,8 @@ Provided clocks:
		21: USB3 ch1 PHY1


		Media I/O (MIO) clock
		---------------------
		Media I/O (MIO) clock, SD clock
		-------------------------------

		Required properties:
		- compatible: should be one of the following:
		@@ -52,10 +52,10 @@ Required properties:
		"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
		"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
		"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
		"socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
		"socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
		"socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
		"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
		"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
		"socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
		"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
		- #clock-cells: should be 1.

		Example:
		@@ -66,7 +66,7 @@ Example:
		reg = <0x59810000 0x800>;

		clock {
		compatible = "socionext,uniphier-ld20-mio-clock";
		compatible = "socionext,uniphier-ld11-mio-clock";
		#clock-cells = <1>;
		};

		@@ -112,7 +112,7 @@ Example:
		reg = <0x59820000 0x200>;

		clock {
		compatible = "socionext,uniphier-ld20-peri-clock";
		compatible = "socionext,uniphier-ld11-peri-clock";
		#clock-cells = <1>;
		};

Documentation/devicetree/bindings/reset/uniphier-reset.txt

+31 −31

Original line number	Diff line number	Diff line
		@@ -6,25 +6,25 @@ System reset

		Required properties:
		- compatible: should be one of the following:
		"socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
		"socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
		"socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
		"socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
		"socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
		"socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
		"socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
		"socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
		"socionext,uniphier-sld3-reset" - for sLD3 SoC.
		"socionext,uniphier-ld4-reset" - for LD4 SoC.
		"socionext,uniphier-pro4-reset" - for Pro4 SoC.
		"socionext,uniphier-sld8-reset" - for sLD8 SoC.
		"socionext,uniphier-pro5-reset" - for Pro5 SoC.
		"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.
		"socionext,uniphier-ld11-reset" - for LD11 SoC.
		"socionext,uniphier-ld20-reset" - for LD20 SoC.
		- #reset-cells: should be 1.

		Example:

		sysctrl@61840000 {
		compatible = "socionext,uniphier-ld20-sysctrl",
		compatible = "socionext,uniphier-ld11-sysctrl",
		"simple-mfd", "syscon";
		reg = <0x61840000 0x4000>;

		reset {
		compatible = "socionext,uniphier-ld20-reset";
		compatible = "socionext,uniphier-ld11-reset";
		#reset-cells = <1>;
		};

		@@ -32,30 +32,30 @@ Example:
		};


		Media I/O (MIO) reset
		---------------------
		Media I/O (MIO) reset, SD reset
		-------------------------------

		Required properties:
		- compatible: should be one of the following:
		"socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
		"socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
		"socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
		"socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
		"socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
		"socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
		"socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
		"socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
		"socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.
		"socionext,uniphier-ld4-mio-reset" - for LD4 SoC.
		"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.
		"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.
		"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC.
		"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC.
		"socionext,uniphier-ld11-mio-reset" - for LD11 SoC.
		"socionext,uniphier-ld20-sd-reset" - for LD20 SoC.
		- #reset-cells: should be 1.

		Example:

		mioctrl@59810000 {
		compatible = "socionext,uniphier-ld20-mioctrl",
		compatible = "socionext,uniphier-ld11-mioctrl",
		"simple-mfd", "syscon";
		reg = <0x59810000 0x800>;

		reset {
		compatible = "socionext,uniphier-ld20-mio-reset";
		compatible = "socionext,uniphier-ld11-mio-reset";
		#reset-cells = <1>;
		};

		@@ -68,24 +68,24 @@ Peripheral reset

		Required properties:
		- compatible: should be one of the following:
		"socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
		"socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
		"socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
		"socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
		"socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
		"socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
		"socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
		"socionext,uniphier-ld4-peri-reset" - for LD4 SoC.
		"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.
		"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.
		"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.
		"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.
		"socionext,uniphier-ld11-peri-reset" - for LD11 SoC.
		"socionext,uniphier-ld20-peri-reset" - for LD20 SoC.
		- #reset-cells: should be 1.

		Example:

		perictrl@59820000 {
		compatible = "socionext,uniphier-ld20-perictrl",
		compatible = "socionext,uniphier-ld11-perictrl",
		"simple-mfd", "syscon";
		reg = <0x59820000 0x200>;

		reset {
		compatible = "socionext,uniphier-ld20-peri-reset";
		compatible = "socionext,uniphier-ld11-peri-reset";
		#reset-cells = <1>;
		};

Documentation/devicetree/bindings/serial/cdns,uart.txt

+3 −1

Original line number	Diff line number	Diff line
		Binding for Cadence UART Controller

		Required properties:
		- compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps"
		- compatible :
		Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
		Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
		- reg: Should contain UART controller registers location and length.
		- interrupts: Should contain UART controller interrupts.
		- clocks: Must contain phandles to the UART clocks