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Commit 50237287 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: various cleanups for uvd/vce.

parent e6707218
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+4 −15
Original line number Diff line number Diff line
@@ -135,12 +135,9 @@ static int uvd_v4_2_sw_fini(void *handle)
	if (r)
		return r;

	r = amdgpu_uvd_sw_fini(adev);
	if (r)
		return r;

	return r;
	return amdgpu_uvd_sw_fini(adev);
}

static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
				 bool enable);
/**
@@ -230,11 +227,7 @@ static int uvd_v4_2_suspend(void *handle)
	if (r)
		return r;

	r = amdgpu_uvd_suspend(adev);
	if (r)
		return r;

	return r;
	return amdgpu_uvd_suspend(adev);
}

static int uvd_v4_2_resume(void *handle)
@@ -246,11 +239,7 @@ static int uvd_v4_2_resume(void *handle)
	if (r)
		return r;

	r = uvd_v4_2_hw_init(adev);
	if (r)
		return r;

	return r;
	return uvd_v4_2_hw_init(adev);
}

/**
+3 −15
Original line number Diff line number Diff line
@@ -131,11 +131,7 @@ static int uvd_v5_0_sw_fini(void *handle)
	if (r)
		return r;

	r = amdgpu_uvd_sw_fini(adev);
	if (r)
		return r;

	return r;
	return amdgpu_uvd_sw_fini(adev);
}

/**
@@ -228,11 +224,7 @@ static int uvd_v5_0_suspend(void *handle)
		return r;
	uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);

	r = amdgpu_uvd_suspend(adev);
	if (r)
		return r;

	return r;
	return amdgpu_uvd_suspend(adev);
}

static int uvd_v5_0_resume(void *handle)
@@ -244,11 +236,7 @@ static int uvd_v5_0_resume(void *handle)
	if (r)
		return r;

	r = uvd_v5_0_hw_init(adev);
	if (r)
		return r;

	return r;
	return uvd_v5_0_hw_init(adev);
}

/**
+3 −14
Original line number Diff line number Diff line
@@ -134,11 +134,7 @@ static int uvd_v6_0_sw_fini(void *handle)
	if (r)
		return r;

	r = amdgpu_uvd_sw_fini(adev);
	if (r)
		return r;

	return r;
	return amdgpu_uvd_sw_fini(adev);
}

/**
@@ -230,11 +226,8 @@ static int uvd_v6_0_suspend(void *handle)
		return r;

	/* Skip this for APU for now */
	if (!(adev->flags & AMD_IS_APU)) {
	if (!(adev->flags & AMD_IS_APU))
		r = amdgpu_uvd_suspend(adev);
		if (r)
			return r;
	}

	return r;
}
@@ -250,11 +243,7 @@ static int uvd_v6_0_resume(void *handle)
		if (r)
			return r;
	}
	r = uvd_v6_0_hw_init(adev);
	if (r)
		return r;

	return r;
	return uvd_v6_0_hw_init(adev);
}

/**
+3 −14
Original line number Diff line number Diff line
@@ -438,11 +438,7 @@ static int uvd_v7_0_sw_fini(void *handle)
	for (i = 0; i < adev->uvd.num_enc_rings; ++i)
		amdgpu_ring_fini(&adev->uvd.ring_enc[i]);

	r = amdgpu_uvd_sw_fini(adev);
	if (r)
		return r;

	return r;
	return amdgpu_uvd_sw_fini(adev);
}

/**
@@ -547,11 +543,8 @@ static int uvd_v7_0_suspend(void *handle)
		return r;

	/* Skip this for APU for now */
	if (!(adev->flags & AMD_IS_APU)) {
	if (!(adev->flags & AMD_IS_APU))
		r = amdgpu_uvd_suspend(adev);
		if (r)
			return r;
	}

	return r;
}
@@ -567,11 +560,7 @@ static int uvd_v7_0_resume(void *handle)
		if (r)
			return r;
	}
	r = uvd_v7_0_hw_init(adev);
	if (r)
		return r;

	return r;
	return uvd_v7_0_hw_init(adev);
}

/**
+3 −15
Original line number Diff line number Diff line
@@ -451,11 +451,7 @@ static int vce_v2_0_sw_fini(void *handle)
	if (r)
		return r;

	r = amdgpu_vce_sw_fini(adev);
	if (r)
		return r;

	return r;
	return amdgpu_vce_sw_fini(adev);
}

static int vce_v2_0_hw_init(void *handle)
@@ -495,11 +491,7 @@ static int vce_v2_0_suspend(void *handle)
	if (r)
		return r;

	r = amdgpu_vce_suspend(adev);
	if (r)
		return r;

	return r;
	return amdgpu_vce_suspend(adev);
}

static int vce_v2_0_resume(void *handle)
@@ -511,11 +503,7 @@ static int vce_v2_0_resume(void *handle)
	if (r)
		return r;

	r = vce_v2_0_hw_init(adev);
	if (r)
		return r;

	return r;
	return vce_v2_0_hw_init(adev);
}

static int vce_v2_0_soft_reset(void *handle)
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