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Commit 50077507 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-next 



More features for 4.19:
- Map processes to vmids for debugging GPUVM faults
- Raven gfxoff fixes
- Initial gfxoff support for vega12
- Use defines for interrupt sources rather than magic numbers
- DC aux fixes
- Finish DC logging TODO
- Add more DC debugfs interfaces for conformance testing
- Add CRC support for DCN
- Scheduler rework in preparation for load balancing
- Unify common smu9 code
- Clean up UVD instancing support
- ttm cleanups
- Misc fixes and cleanups

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180719194001.3488-1-alexander.deucher@amd.com
parents ef8e0ff9 5c675bf2

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+14 −51
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ 
#include "amdgpu_virt.h"

#include "amdgpu_gart.h"

#include "amdgpu_debugfs.h"

#include "amdgpu_job.h"



/*

 * Modules parameters.
@@ -105,11 +106,8 @@ extern int amdgpu_vm_fault_stop; 
extern int amdgpu_vm_debug;

extern int amdgpu_vm_update_mode;

extern int amdgpu_dc;

extern int amdgpu_dc_log;

extern int amdgpu_sched_jobs;

extern int amdgpu_sched_hw_submission;

extern int amdgpu_no_evict;

extern int amdgpu_direct_gma_size;

extern uint amdgpu_pcie_gen_cap;

extern uint amdgpu_pcie_lane_cap;

extern uint amdgpu_cg_mask;
@@ -600,17 +598,6 @@ struct amdgpu_ib { 


extern const struct drm_sched_backend_ops amdgpu_sched_ops;



int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,

		     struct amdgpu_job **job, struct amdgpu_vm *vm);

int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

			     struct amdgpu_job **job);



void amdgpu_job_free_resources(struct amdgpu_job *job);

void amdgpu_job_free(struct amdgpu_job *job);

int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,

		      struct drm_sched_entity *entity, void *owner,

		      struct dma_fence **f);



/*

 * Queue manager

 */
@@ -732,6 +719,14 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 
			     struct list_head *validated);

void amdgpu_bo_list_put(struct amdgpu_bo_list *list);

void amdgpu_bo_list_free(struct amdgpu_bo_list *list);

int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,

				      struct drm_amdgpu_bo_list_entry **info_param);



int amdgpu_bo_list_create(struct amdgpu_device *adev,

				 struct drm_file *filp,

				 struct drm_amdgpu_bo_list_entry *info,

				 unsigned num_entries,

				 struct amdgpu_bo_list **list);



/*

 * GFX stuff
@@ -1029,6 +1024,7 @@ struct amdgpu_cs_parser { 


	/* scheduler job object */

	struct amdgpu_job	*job;

	struct amdgpu_ring	*ring;



	/* buffer objects */

	struct ww_acquire_ctx		ticket;
@@ -1050,40 +1046,6 @@ struct amdgpu_cs_parser { 
	struct drm_syncobj **post_dep_syncobjs;

};



#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */

#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */

#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */



struct amdgpu_job {

	struct drm_sched_job    base;

	struct amdgpu_device	*adev;

	struct amdgpu_vm	*vm;

	struct amdgpu_ring	*ring;

	struct amdgpu_sync	sync;

	struct amdgpu_sync	sched_sync;

	struct amdgpu_ib	*ibs;

	struct dma_fence	*fence; /* the hw fence */

	uint32_t		preamble_status;

	uint32_t		num_ibs;

	void			*owner;

	uint64_t		fence_ctx; /* the fence_context this job uses */

	bool                    vm_needs_flush;

	uint64_t		vm_pd_addr;

	unsigned		vmid;

	unsigned		pasid;

	uint32_t		gds_base, gds_size;

	uint32_t		gws_base, gws_size;

	uint32_t		oa_base, oa_size;

	uint32_t		vram_lost_counter;



	/* user fence handling */

	uint64_t		uf_addr;

	uint64_t		uf_sequence;



};

#define to_amdgpu_job(sched_job)		\

		container_of((sched_job), struct amdgpu_job, base)



static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,

				      uint32_t ib_idx, int idx)

{
@@ -1398,6 +1360,7 @@ enum amd_hw_ip_block_type { 
	PWR_HWIP,

	NBIF_HWIP,

	THM_HWIP,

	CLK_HWIP,

	MAX_HWIP

};
@@ -1588,9 +1551,9 @@ struct amdgpu_device { 
	DECLARE_HASHTABLE(mn_hash, 7);



	/* tracking pinned memory */

	u64 vram_pin_size;

	u64 invisible_pin_size;

	u64 gart_pin_size;

	atomic64_t vram_pin_size;

	atomic64_t visible_pin_size;

	atomic64_t gart_pin_size;



	/* amdkfd interface */

	struct kfd_dev          *kfd;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+8 −4
Original line number Diff line number Diff line
@@ -251,7 +251,6 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 
	struct amdgpu_bo *bo = NULL;

	struct amdgpu_bo_param bp;

	int r;

	uint64_t gpu_addr_tmp = 0;

	void *cpu_ptr_tmp = NULL;



	memset(&bp, 0, sizeof(bp));
@@ -275,13 +274,18 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 
		goto allocate_mem_reserve_bo_failed;

	}



	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT,

				&gpu_addr_tmp);

	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);

	if (r) {

		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);

		goto allocate_mem_pin_bo_failed;

	}



	r = amdgpu_ttm_alloc_gart(&bo->tbo);

	if (r) {

		dev_err(adev->dev, "%p bind failed\n", bo);

		goto allocate_mem_kmap_bo_failed;

	}



	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);

	if (r) {

		dev_err(adev->dev,
@@ -290,7 +294,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 
	}



	*mem_obj = bo;

	*gpu_addr = gpu_addr_tmp;

	*gpu_addr = amdgpu_bo_gpu_offset(bo);

	*cpu_ptr = cpu_ptr_tmp;



	amdgpu_bo_unreserve(bo);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+1 −1
Original line number Diff line number Diff line
@@ -1587,7 +1587,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd, 
		goto bo_reserve_failed;

	}



	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);

	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);

	if (ret) {

		pr_err("Failed to pin bo. ret %d\n", ret);

		goto pin_failed;

drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c

+14 −2
Original line number Diff line number Diff line
@@ -95,11 +95,17 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, 
	r = amdgpu_bo_reserve(sobj, false);

	if (unlikely(r != 0))

		goto out_cleanup;

	r = amdgpu_bo_pin(sobj, sdomain, &saddr);

	r = amdgpu_bo_pin(sobj, sdomain);

	if (r) {

		amdgpu_bo_unreserve(sobj);

		goto out_cleanup;

	}

	r = amdgpu_ttm_alloc_gart(&sobj->tbo);

	amdgpu_bo_unreserve(sobj);

	if (r) {

		goto out_cleanup;

	}

	saddr = amdgpu_bo_gpu_offset(sobj);

	bp.domain = ddomain;

	r = amdgpu_bo_create(adev, &bp, &dobj);

	if (r) {
@@ -108,11 +114,17 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, 
	r = amdgpu_bo_reserve(dobj, false);

	if (unlikely(r != 0))

		goto out_cleanup;

	r = amdgpu_bo_pin(dobj, ddomain, &daddr);

	r = amdgpu_bo_pin(dobj, ddomain);

	if (r) {

		amdgpu_bo_unreserve(sobj);

		goto out_cleanup;

	}

	r = amdgpu_ttm_alloc_gart(&dobj->tbo);

	amdgpu_bo_unreserve(dobj);

	if (r) {

		goto out_cleanup;

	}

	daddr = amdgpu_bo_gpu_offset(dobj);



	if (adev->mman.buffer_funcs) {

		time = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c

+52 −36
Original line number Diff line number Diff line
@@ -55,15 +55,15 @@ static void amdgpu_bo_list_release_rcu(struct kref *ref) 
	kfree_rcu(list, rhead);

}



static int amdgpu_bo_list_create(struct amdgpu_device *adev,

int amdgpu_bo_list_create(struct amdgpu_device *adev,

				 struct drm_file *filp,

				 struct drm_amdgpu_bo_list_entry *info,

				 unsigned num_entries,

				 int *id)

				 struct amdgpu_bo_list **list_out)

{

	int r;

	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	struct amdgpu_bo_list *list;

	int r;





	list = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL);

	if (!list)
@@ -78,16 +78,7 @@ static int amdgpu_bo_list_create(struct amdgpu_device *adev, 
		return r;

	}



	/* idr alloc should be called only after initialization of bo list. */

	mutex_lock(&fpriv->bo_list_lock);

	r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);

	mutex_unlock(&fpriv->bo_list_lock);

	if (r < 0) {

		amdgpu_bo_list_free(list);

		return r;

	}

	*id = r;



	*list_out = list;

	return 0;

}
@@ -263,55 +254,79 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list) 
	kfree(list);

}



int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,

				struct drm_file *filp)

int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,

				      struct drm_amdgpu_bo_list_entry **info_param)

{

	const void __user *uptr = u64_to_user_ptr(in->bo_info_ptr);

	const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry);



	struct amdgpu_device *adev = dev->dev_private;

	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	union drm_amdgpu_bo_list *args = data;

	uint32_t handle = args->in.list_handle;

	const void __user *uptr = u64_to_user_ptr(args->in.bo_info_ptr);



	struct drm_amdgpu_bo_list_entry *info;

	struct amdgpu_bo_list *list;



	int r;



	info = kvmalloc_array(args->in.bo_number,

			     sizeof(struct drm_amdgpu_bo_list_entry), GFP_KERNEL);

	info = kvmalloc_array(in->bo_number, info_size, GFP_KERNEL);

	if (!info)

		return -ENOMEM;



	/* copy the handle array from userspace to a kernel buffer */

	r = -EFAULT;

	if (likely(info_size == args->in.bo_info_size)) {

		unsigned long bytes = args->in.bo_number *

			args->in.bo_info_size;

	if (likely(info_size == in->bo_info_size)) {

		unsigned long bytes = in->bo_number *

			in->bo_info_size;



		if (copy_from_user(info, uptr, bytes))

			goto error_free;



	} else {

		unsigned long bytes = min(args->in.bo_info_size, info_size);

		unsigned long bytes = min(in->bo_info_size, info_size);

		unsigned i;



		memset(info, 0, args->in.bo_number * info_size);

		for (i = 0; i < args->in.bo_number; ++i) {

		memset(info, 0, in->bo_number * info_size);

		for (i = 0; i < in->bo_number; ++i) {

			if (copy_from_user(&info[i], uptr, bytes))

				goto error_free;



			uptr += args->in.bo_info_size;

			uptr += in->bo_info_size;

		}

	}



	*info_param = info;

	return 0;



error_free:

	kvfree(info);

	return r;

}



int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,

				struct drm_file *filp)

{

	struct amdgpu_device *adev = dev->dev_private;

	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	union drm_amdgpu_bo_list *args = data;

	uint32_t handle = args->in.list_handle;

	struct drm_amdgpu_bo_list_entry *info = NULL;

	struct amdgpu_bo_list *list;

	int r;



	r = amdgpu_bo_create_list_entry_array(&args->in, &info);

	if (r)

		goto error_free;



	switch (args->in.operation) {

	case AMDGPU_BO_LIST_OP_CREATE:

		r = amdgpu_bo_list_create(adev, filp, info, args->in.bo_number,

					  &handle);

					  &list);

		if (r)

			goto error_free;



		mutex_lock(&fpriv->bo_list_lock);

		r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);

		mutex_unlock(&fpriv->bo_list_lock);

		if (r < 0) {

			amdgpu_bo_list_free(list);

			return r;

		}



		handle = r;

		break;



	case AMDGPU_BO_LIST_OP_DESTROY:
@@ -345,6 +360,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 
	return 0;



error_free:

	if (info)

		kvfree(info);

	return r;

}