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Commit 4fe9676d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next' of ../drm-2.6 into drm-next

parents 273fad2b e29649db

drivers/gpu/drm/radeon/r100.c

+6 −6
Original line number Diff line number Diff line
@@ -578,19 +578,19 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 
	indirect1_start = 16;

	/* cp setup */

	WREG32(0x718, pre_write_timer | (pre_write_limit << 28));

	WREG32(RADEON_CP_RB_CNTL,

#ifdef __BIG_ENDIAN

	       RADEON_BUF_SWAP_32BIT |

#endif

	       REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |

	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |

	       REG_SET(RADEON_RB_BLKSZ, rb_blksz) |

	       REG_SET(RADEON_MAX_FETCH, max_fetch) |

	       RADEON_RB_NO_UPDATE);

#ifdef __BIG_ENDIAN

	tmp |= RADEON_BUF_SWAP_32BIT;

#endif

	WREG32(RADEON_CP_RB_CNTL, tmp);



	/* Set ring address */

	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);

	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);

	/* Force read & write ptr to 0 */

	tmp = RREG32(RADEON_CP_RB_CNTL);

	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);

	WREG32(RADEON_CP_RB_RPTR_WR, 0);

	WREG32(RADEON_CP_RB_WPTR, 0);

drivers/gpu/drm/radeon/r600.c

+22 −30
Original line number Diff line number Diff line
@@ -409,10 +409,9 @@ int r600_mc_init(struct radeon_device *rdev) 
			rdev->mc.gtt_location = rdev->mc.mc_vram_size;

		}

	} else {

		if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {

		rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;

		rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &

							0xFFFF) << 24;

			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;

		tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;

		if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {

			/* Enough place after vram */
@@ -433,11 +432,6 @@ int r600_mc_init(struct radeon_device *rdev) 
			}

		}

		rdev->mc.gtt_location = rdev->mc.mc_vram_size;

		} else {

			rdev->mc.vram_location = 0x00000000UL;

			rdev->mc.gtt_location = rdev->mc.mc_vram_size;

			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;

		}

	}

	rdev->mc.vram_start = rdev->mc.vram_location;

	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
@@ -1272,19 +1266,17 @@ int r600_cp_resume(struct radeon_device *rdev) 


	/* Set ring buffer size */

	rb_bufsz = drm_order(rdev->cp.ring_size / 8);

	tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN

	WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |

		(drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz);

#else

	WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz);

	tmp |= BUF_SWAP_32BIT;

#endif

	WREG32(CP_RB_CNTL, tmp);

	WREG32(CP_SEM_WAIT_TIMER, 0x4);



	/* Set the write pointer delay */

	WREG32(CP_RB_WPTR_DELAY, 0);



	/* Initialize the ring buffer's read and write pointers */

	tmp = RREG32(CP_RB_CNTL);

	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB_RPTR_WR, 0);

	WREG32(CP_RB_WPTR, 0);

drivers/gpu/drm/radeon/radeon_bios.c

+0 −3
Original line number Diff line number Diff line
@@ -50,19 +50,16 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev) 
	vram_base = drm_get_resource_start(rdev->ddev, 0);

	bios = ioremap(vram_base, size);

	if (!bios) {

		DRM_ERROR("Unable to mmap vram\n");

		return false;

	}



	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {

		iounmap(bios);

		DRM_ERROR("bad rom signature\n");

		return false;

	}

	rdev->bios = kmalloc(size, GFP_KERNEL);

	if (rdev->bios == NULL) {

		iounmap(bios);

		DRM_ERROR("kmalloc failed\n");

		return false;

	}

	memcpy(rdev->bios, bios, size);

drivers/gpu/drm/radeon/radeon_ttm.c

+6 −0
Original line number Diff line number Diff line
@@ -295,6 +295,12 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 
	if (unlikely(r)) {

		return r;

	}



	r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);

	if (unlikely(r)) {

		goto out_cleanup;

	}



	r = ttm_tt_bind(bo->ttm, &tmp_mem);

	if (unlikely(r)) {

		goto out_cleanup;

drivers/gpu/drm/radeon/rv515.c

+2 −0
Original line number Diff line number Diff line
@@ -137,6 +137,8 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev) 


void rv515_vga_render_disable(struct radeon_device *rdev)

{

	WREG32(R_000330_D1VGA_CONTROL, 0);

	WREG32(R_000338_D2VGA_CONTROL, 0);

	WREG32(R_000300_VGA_RENDER_CONTROL,

		RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);

}