Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4f9faaac authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (47 commits)
  rose: Wrong list_lock argument in rose_node seqops
  netns: Fix reassembly timer to use the right namespace
  netns: Fix device renaming for sysfs
  bnx2: Update version to 1.7.5.
  bnx2: Update RV2P firmware for 5709.
  bnx2: Zero out context memory for 5709.
  bnx2: Fix register test on 5709.
  bnx2: Fix remote PHY initial link state.
  bnx2: Refine remote PHY locking.
  bridge: forwarding table information for >256 devices
  tg3: Update version to 3.92
  tg3: Add link state reporting to UMP firmware
  tg3: Fix ethtool loopback test for 5761 BX devices
  tg3: Fix 5761 NVRAM sizes
  tg3: Use constant 500KHz MI clock on adapters with a CPMU
  hci_usb.h: fix hard-to-trigger race
  dccp: ccid2.c, ccid3.c use clamp(), clamp_t()
  net: remove NR_CPUS arrays in net/core/dev.c
  net: use get/put_unaligned_* helpers
  bluetooth: use get/put_unaligned_* helpers
  ...
parents bf640be4 f37f2c62

drivers/bluetooth/hci_usb.h

+13 −8
Original line number Diff line number Diff line
@@ -70,7 +70,8 @@ static inline void _urb_queue_head(struct _urb_queue *q, struct _urb *_urb) 
{

	unsigned long flags;

	spin_lock_irqsave(&q->lock, flags);

	list_add(&_urb->list, &q->head); _urb->queue = q;

	/* _urb_unlink needs to know which spinlock to use, thus mb(). */

	_urb->queue = q; mb(); list_add(&_urb->list, &q->head);

	spin_unlock_irqrestore(&q->lock, flags);

}
@@ -78,20 +79,24 @@ static inline void _urb_queue_tail(struct _urb_queue *q, struct _urb *_urb) 
{

	unsigned long flags;

	spin_lock_irqsave(&q->lock, flags);

	list_add_tail(&_urb->list, &q->head); _urb->queue = q;

	/* _urb_unlink needs to know which spinlock to use, thus mb(). */

	_urb->queue = q; mb(); list_add_tail(&_urb->list, &q->head);

	spin_unlock_irqrestore(&q->lock, flags);

}



static inline void _urb_unlink(struct _urb *_urb)

{

	struct _urb_queue *q = _urb->queue;

	struct _urb_queue *q;

	unsigned long flags;

	if (q) {



	mb();

	q = _urb->queue;

	/* If q is NULL, it will die at easy-to-debug NULL pointer dereference.

	   No need to BUG(). */

	spin_lock_irqsave(&q->lock, flags);

	list_del(&_urb->list); _urb->queue = NULL;

	spin_unlock_irqrestore(&q->lock, flags);

}

}



struct hci_usb {

	struct hci_dev		*hdev;

drivers/net/8390.c

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ struct net_device *__alloc_ei_netdev(int size) 


void NS8390_init(struct net_device *dev, int startp)

{

	return __NS8390_init(dev, startp);

	__NS8390_init(dev, startp);

}



EXPORT_SYMBOL(ei_open);

drivers/net/bnx2.c

+25 −18
Original line number Diff line number Diff line
@@ -56,8 +56,8 @@ 


#define DRV_MODULE_NAME		"bnx2"

#define PFX DRV_MODULE_NAME	": "

#define DRV_MODULE_VERSION	"1.7.4"

#define DRV_MODULE_RELDATE	"February 18, 2008"

#define DRV_MODULE_VERSION	"1.7.5"

#define DRV_MODULE_RELDATE	"April 29, 2008"



#define RUN_AT(x) (jiffies + (x))
@@ -1631,8 +1631,10 @@ bnx2_set_default_remote_link(struct bnx2 *bp) 
static void

bnx2_set_default_link(struct bnx2 *bp)

{

	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)

		return bnx2_set_default_remote_link(bp);

	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {

		bnx2_set_default_remote_link(bp);

		return;

	}



	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;

	bp->req_line_speed = 0;
@@ -1715,7 +1717,6 @@ bnx2_remote_phy_event(struct bnx2 *bp) 
				break;

		}



		spin_lock(&bp->phy_lock);

		bp->flow_ctrl = 0;

		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=

		    (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
@@ -1737,7 +1738,6 @@ bnx2_remote_phy_event(struct bnx2 *bp) 
		if (old_port != bp->phy_port)

			bnx2_set_default_link(bp);



		spin_unlock(&bp->phy_lock);

	}

	if (bp->link_up != link_up)

		bnx2_report_link(bp);
@@ -2222,6 +2222,11 @@ bnx2_init_5709_context(struct bnx2 *bp) 
	for (i = 0; i < bp->ctx_pages; i++) {

		int j;



		if (bp->ctx_blk[i])

			memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);

		else

			return -ENOMEM;



		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,

		       (bp->ctx_blk_mapping[i] & 0xffffffff) |

		       BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
@@ -2445,14 +2450,15 @@ bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) 
static void

bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)

{

	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) {

	spin_lock(&bp->phy_lock);



	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))

		bnx2_set_link(bp);

		spin_unlock(&bp->phy_lock);

	}

	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))

		bnx2_set_remote_link(bp);



	spin_unlock(&bp->phy_lock);



}



static inline u16
@@ -3174,6 +3180,12 @@ load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len, 
	int i;

	u32 val;



	if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {

		val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);

		val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;

		val |= XI_RV2P_PROC2_BD_PAGE_SIZE;

		rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);

	}



	for (i = 0; i < rv2p_code_len; i += 8) {

		REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
@@ -4215,13 +4227,6 @@ bnx2_init_remote_phy(struct bnx2 *bp) 
		if (netif_running(bp->dev)) {

			u32 sig;



			if (val & BNX2_LINK_STATUS_LINK_UP) {

				bp->link_up = 1;

				netif_carrier_on(bp->dev);

			} else {

				bp->link_up = 0;

				netif_carrier_off(bp->dev);

			}

			sig = BNX2_DRV_ACK_CAP_SIGNATURE |

			      BNX2_FW_CAP_REMOTE_PHY_CAPABLE;

			bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
@@ -4878,6 +4883,8 @@ bnx2_init_nic(struct bnx2 *bp) 
	spin_lock_bh(&bp->phy_lock);

	bnx2_init_phy(bp);

	bnx2_set_link(bp);

	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)

		bnx2_remote_phy_event(bp);

	spin_unlock_bh(&bp->phy_lock);

	return 0;

}
@@ -4920,7 +4927,7 @@ bnx2_test_registers(struct bnx2 *bp) 
		{ 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },



		{ 0x1000, 0, 0x00000000, 0x00000001 },

		{ 0x1004, 0, 0x00000000, 0x000f0001 },

		{ 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },



		{ 0x1408, 0, 0x01c00800, 0x00000000 },

		{ 0x149c, 0, 0x8000ffff, 0x00000000 },

drivers/net/bnx2_fw2.h

+259 −243

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/tg3.c

+113 −36
Original line number Diff line number Diff line
@@ -64,8 +64,8 @@ 


#define DRV_MODULE_NAME		"tg3"

#define PFX DRV_MODULE_NAME	": "

#define DRV_MODULE_VERSION	"3.91"

#define DRV_MODULE_RELDATE	"April 18, 2008"

#define DRV_MODULE_VERSION	"3.92"

#define DRV_MODULE_RELDATE	"May 2, 2008"



#define TG3_DEF_MAC_MODE	0

#define TG3_DEF_RX_MODE		0
@@ -1656,12 +1656,76 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) 
	return 0;

}



/* tp->lock is held. */

static void tg3_wait_for_event_ack(struct tg3 *tp)

{

	int i;



	/* Wait for up to 2.5 milliseconds */

	for (i = 0; i < 250000; i++) {

		if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))

			break;

		udelay(10);

	}

}



/* tp->lock is held. */

static void tg3_ump_link_report(struct tg3 *tp)

{

	u32 reg;

	u32 val;



	if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||

	    !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))

		return;



	tg3_wait_for_event_ack(tp);



	tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);



	tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);



	val = 0;

	if (!tg3_readphy(tp, MII_BMCR, &reg))

		val = reg << 16;

	if (!tg3_readphy(tp, MII_BMSR, &reg))

		val |= (reg & 0xffff);

	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);



	val = 0;

	if (!tg3_readphy(tp, MII_ADVERTISE, &reg))

		val = reg << 16;

	if (!tg3_readphy(tp, MII_LPA, &reg))

		val |= (reg & 0xffff);

	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);



	val = 0;

	if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {

		if (!tg3_readphy(tp, MII_CTRL1000, &reg))

			val = reg << 16;

		if (!tg3_readphy(tp, MII_STAT1000, &reg))

			val |= (reg & 0xffff);

	}

	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);



	if (!tg3_readphy(tp, MII_PHYADDR, &reg))

		val = reg << 16;

	else

		val = 0;

	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);



	val = tr32(GRC_RX_CPU_EVENT);

	val |= GRC_RX_CPU_DRIVER_EVENT;

	tw32_f(GRC_RX_CPU_EVENT, val);

}



static void tg3_link_report(struct tg3 *tp)

{

	if (!netif_carrier_ok(tp->dev)) {

		if (netif_msg_link(tp))

			printk(KERN_INFO PFX "%s: Link is down.\n",

			       tp->dev->name);

		tg3_ump_link_report(tp);

	} else if (netif_msg_link(tp)) {

		printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",

		       tp->dev->name,
@@ -1679,6 +1743,7 @@ static void tg3_link_report(struct tg3 *tp) 
		       "on" : "off",

		       (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?

		       "on" : "off");

		tg3_ump_link_report(tp);

	}

}
@@ -2097,9 +2162,11 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) 
	      MAC_STATUS_LNKSTATE_CHANGED));

	udelay(40);



	tp->mi_mode = MAC_MI_MODE_BASE;

	tw32_f(MAC_MI_MODE, tp->mi_mode);

	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {

		tw32_f(MAC_MI_MODE,

		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));

		udelay(80);

	}



	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
@@ -5498,19 +5565,17 @@ static void tg3_stop_fw(struct tg3 *tp) 
	if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&

	   !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {

		u32 val;

		int i;



		/* Wait for RX cpu to ACK the previous event. */

		tg3_wait_for_event_ack(tp);



		tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);

		val = tr32(GRC_RX_CPU_EVENT);

		val |= (1 << 14);

		val |= GRC_RX_CPU_DRIVER_EVENT;

		tw32(GRC_RX_CPU_EVENT, val);



		/* Wait for RX cpu to ACK the event.  */

		for (i = 0; i < 100; i++) {

			if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))

				break;

			udelay(1);

		}

		/* Wait for RX cpu to ACK this event. */

		tg3_wait_for_event_ack(tp);

	}

}
@@ -7102,7 +7167,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		tp->link_config.autoneg = tp->link_config.orig_autoneg;

	}



	tp->mi_mode = MAC_MI_MODE_BASE;

	tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;

	tw32_f(MAC_MI_MODE, tp->mi_mode);

	udelay(80);
@@ -7400,14 +7465,16 @@ static void tg3_timer(unsigned long __opaque) 
		if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {

			u32 val;



			tg3_wait_for_event_ack(tp);



			tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,

				      FWCMD_NICDRV_ALIVE3);

			tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);

			/* 5 seconds timeout */

			tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);

			val = tr32(GRC_RX_CPU_EVENT);

			val |= (1 << 14);

			tw32(GRC_RX_CPU_EVENT, val);

			val |= GRC_RX_CPU_DRIVER_EVENT;

			tw32_f(GRC_RX_CPU_EVENT, val);

		}

		tp->asf_counter = tp->asf_multiplier;

	}
@@ -9568,14 +9635,9 @@ static int tg3_test_loopback(struct tg3 *tp) 


		/* Turn off link-based power management. */

		cpmuctrl = tr32(TG3_CPMU_CTRL);

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||

		    GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX)

		tw32(TG3_CPMU_CTRL,

		     cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |

				  CPMU_CTRL_LINK_AWARE_MODE));

		else

			tw32(TG3_CPMU_CTRL,

			     cpmuctrl & ~CPMU_CTRL_LINK_AWARE_MODE);

	}



	if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
@@ -9892,7 +9954,7 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp) 
			return;

		}

	}

	tp->nvram_size = 0x80000;

	tp->nvram_size = TG3_NVRAM_SIZE_512KB;

}



static void __devinit tg3_get_nvram_info(struct tg3 *tp)
@@ -10033,11 +10095,14 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) 
			tp->nvram_pagesize = 264;

			if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||

			    nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)

				tp->nvram_size = (protect ? 0x3e200 : 0x80000);

				tp->nvram_size = (protect ? 0x3e200 :

						  TG3_NVRAM_SIZE_512KB);

			else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)

				tp->nvram_size = (protect ? 0x1f200 : 0x40000);

				tp->nvram_size = (protect ? 0x1f200 :

						  TG3_NVRAM_SIZE_256KB);

			else

				tp->nvram_size = (protect ? 0x1f200 : 0x20000);

				tp->nvram_size = (protect ? 0x1f200 :

						  TG3_NVRAM_SIZE_128KB);

			break;

		case FLASH_5752VENDOR_ST_M45PE10:

		case FLASH_5752VENDOR_ST_M45PE20:
@@ -10047,11 +10112,17 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) 
			tp->tg3_flags2 |= TG3_FLG2_FLASH;

			tp->nvram_pagesize = 256;

			if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)

				tp->nvram_size = (protect ? 0x10000 : 0x20000);

				tp->nvram_size = (protect ?

						  TG3_NVRAM_SIZE_64KB :

						  TG3_NVRAM_SIZE_128KB);

			else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)

				tp->nvram_size = (protect ? 0x10000 : 0x40000);

				tp->nvram_size = (protect ?

						  TG3_NVRAM_SIZE_64KB :

						  TG3_NVRAM_SIZE_256KB);

			else

				tp->nvram_size = (protect ? 0x20000 : 0x80000);

				tp->nvram_size = (protect ?

						  TG3_NVRAM_SIZE_128KB :

						  TG3_NVRAM_SIZE_512KB);

			break;

	}

}
@@ -10145,25 +10216,25 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) 
			case FLASH_5761VENDOR_ATMEL_MDB161D:

			case FLASH_5761VENDOR_ST_A_M45PE16:

			case FLASH_5761VENDOR_ST_M_M45PE16:

				tp->nvram_size = 0x100000;

				tp->nvram_size = TG3_NVRAM_SIZE_2MB;

				break;

			case FLASH_5761VENDOR_ATMEL_ADB081D:

			case FLASH_5761VENDOR_ATMEL_MDB081D:

			case FLASH_5761VENDOR_ST_A_M45PE80:

			case FLASH_5761VENDOR_ST_M_M45PE80:

				tp->nvram_size = 0x80000;

				tp->nvram_size = TG3_NVRAM_SIZE_1MB;

				break;

			case FLASH_5761VENDOR_ATMEL_ADB041D:

			case FLASH_5761VENDOR_ATMEL_MDB041D:

			case FLASH_5761VENDOR_ST_A_M45PE40:

			case FLASH_5761VENDOR_ST_M_M45PE40:

				tp->nvram_size = 0x40000;

				tp->nvram_size = TG3_NVRAM_SIZE_512KB;

				break;

			case FLASH_5761VENDOR_ATMEL_ADB021D:

			case FLASH_5761VENDOR_ATMEL_MDB021D:

			case FLASH_5761VENDOR_ST_A_M45PE20:

			case FLASH_5761VENDOR_ST_M_M45PE20:

				tp->nvram_size = 0x20000;

				tp->nvram_size = TG3_NVRAM_SIZE_256KB;

				break;

		}

	}
@@ -11764,6 +11835,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
			tp->phy_otp = TG3_OTP_DEFAULT;

	}



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)

		tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;

	else

		tp->mi_mode = MAC_MI_MODE_BASE;



	tp->coalesce_mode = 0;

	if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&

	    GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
@@ -12692,7 +12769,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, 
	tp->mac_mode = TG3_DEF_MAC_MODE;

	tp->rx_mode = TG3_DEF_RX_MODE;

	tp->tx_mode = TG3_DEF_TX_MODE;

	tp->mi_mode = MAC_MI_MODE_BASE;



	if (tg3_debug > 0)

		tp->msg_enable = tg3_debug;

	else