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Commit 4e898ce7 authored by Allen Xu's avatar Allen Xu Committed by Brian Norris
Browse files

mtd: fsl-quadspi: improve read performance by increase AHB transfer size 



Set AHB transfer size to 1K which improved the read performance.

Add ahb_buf_size field in fsl_qspi_devtype_data to denote the size for
different SoC.

Before:

root@imx6qdlsolo:~# dd if=/dev/mtd1 of=/dev/null bs=1M count=16
16+0 records in
16+0 records out
16777216 bytes (17 MB) copied, 0.472183 s, 25.1 MB/s

After:

root@imx6qdlsolo:~# dd if=/dev/mtd1 of=/dev/null bs=1M count=16
16+0 records in
16+0 records out
16777216 bytes (17 MB) copied, 0.369439 s, 29.5 MB/s

Signed-off-by: default avatarAllen Xu <b45815@freescale.com>
Signed-off-by: default avatarHuang Shijie <shijie8@gmail.com>
Signed-off-by: default avatarFrank Li <Frank.Li@freescale.com>
Acked-by: default avatarHuang Shijie <shijie.huang@intel.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent b1ab474f

drivers/mtd/spi-nor/fsl-quadspi.c

+14 −4
Original line number Original line Diff line number Diff line
@@ -57,7 +57,9 @@ 




#define QUADSPI_BUF3CR			0x1c

#define QUADSPI_BUF3CR			0x1c

#define QUADSPI_BUF3CR_ALLMST_SHIFT	31

#define QUADSPI_BUF3CR_ALLMST_SHIFT	31

#define QUADSPI_BUF3CR_ALLMST		(1 << QUADSPI_BUF3CR_ALLMST_SHIFT)

#define QUADSPI_BUF3CR_ALLMST_MASK	(1 << QUADSPI_BUF3CR_ALLMST_SHIFT)

#define QUADSPI_BUF3CR_ADATSZ_SHIFT		8

#define QUADSPI_BUF3CR_ADATSZ_MASK	(0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)





#define QUADSPI_BFGENCR			0x20

#define QUADSPI_BFGENCR			0x20

#define QUADSPI_BFGENCR_PAR_EN_SHIFT	16

#define QUADSPI_BFGENCR_PAR_EN_SHIFT	16
@@ -198,18 +200,21 @@ struct fsl_qspi_devtype_data { 
	enum fsl_qspi_devtype devtype;

	enum fsl_qspi_devtype devtype;

	int rxfifo;

	int rxfifo;

	int txfifo;

	int txfifo;

	int ahb_buf_size;

};

};





static struct fsl_qspi_devtype_data vybrid_data = {

static struct fsl_qspi_devtype_data vybrid_data = {

	.devtype = FSL_QUADSPI_VYBRID,

	.devtype = FSL_QUADSPI_VYBRID,

	.rxfifo = 128,

	.rxfifo = 128,

	.txfifo = 64

	.txfifo = 64,

	.ahb_buf_size = 1024

};

};





static struct fsl_qspi_devtype_data imx6sx_data = {

static struct fsl_qspi_devtype_data imx6sx_data = {

	.devtype = FSL_QUADSPI_IMX6SX,

	.devtype = FSL_QUADSPI_IMX6SX,

	.rxfifo = 128,

	.rxfifo = 128,

	.txfifo = 512

	.txfifo = 512,

	.ahb_buf_size = 1024

};

};





#define FSL_QSPI_MAX_CHIP	4

#define FSL_QSPI_MAX_CHIP	4
@@ -584,7 +589,12 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) 
	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);

	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);

	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);

	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);

	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);

	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);

	writel(QUADSPI_BUF3CR_ALLMST, base + QUADSPI_BUF3CR);

	/*

	 * Set ADATSZ with the maximum AHB buffer size to improve the

	 * read performance.

	 */

	writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)

			<< QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);





	/* We only use the buffer3 */

	/* We only use the buffer3 */

	writel(0, base + QUADSPI_BUF0IND);

	writel(0, base + QUADSPI_BUF0IND);