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Commit 4e88a862 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
Browse files

MIPS: Add cases for CPU_I6400 



Add a CPU_I6400 case to various switch statements, doing the same thing
as for CPU_P5600.

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10635/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 90b8baa2

arch/mips/include/asm/cpu-type.h

+4 −0
Original line number Diff line number Diff line
@@ -77,6 +77,10 @@ static inline int __pure __get_cpu_type(const int cpu_type) 
	 */

#endif



#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6

	case CPU_I6400:

#endif



#ifdef CONFIG_SYS_HAS_CPU_R3000

	case CPU_R2000:

	case CPU_R3000:

arch/mips/kernel/idle.c

+1 −0
Original line number Diff line number Diff line
@@ -196,6 +196,7 @@ void __init check_wait(void) 
	case CPU_INTERAPTIV:

	case CPU_M5150:

	case CPU_QEMU_GENERIC:

	case CPU_I6400:

		cpu_wait = r4k_wait;

		if (read_c0_config7() & MIPS_CONF7_WII)

			cpu_wait = r4k_wait_irqoff;

arch/mips/kernel/perf_event_mipsxx.c

+6 −0
Original line number Diff line number Diff line
@@ -1556,6 +1556,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) 
#endif

		break;

	case CPU_P5600:

	case CPU_I6400:

		/* 8-bit event numbers */

		raw_id = config & 0x1ff;

		base_id = raw_id & 0xff;
@@ -1717,6 +1718,11 @@ init_hw_perf_events(void) 
		mipspmu.general_event_map = &mipsxxcore_event_map2;

		mipspmu.cache_event_map = &mipsxxcore_cache_map2;

		break;

	case CPU_I6400:

		mipspmu.name = "mips/I6400";

		mipspmu.general_event_map = &mipsxxcore_event_map2;

		mipspmu.cache_event_map = &mipsxxcore_cache_map2;

		break;

	case CPU_1004K:

		mipspmu.name = "mips/1004K";

		mipspmu.general_event_map = &mipsxxcore_event_map;

arch/mips/kernel/pm-cps.c

+2 −0
Original line number Diff line number Diff line
@@ -267,6 +267,7 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl, 


	/* CPUs which do not require the workaround */

	case CPU_P5600:

	case CPU_I6400:

		return 0;



	default:
@@ -671,6 +672,7 @@ static int __init cps_pm_init(void) 
	case CPU_PROAPTIV:

	case CPU_M5150:

	case CPU_P5600:

	case CPU_I6400:

		stype_intervention = 0x2;

		stype_memory = 0x3;

		stype_ordering = 0x10;

arch/mips/kernel/spram.c

+1 −0
Original line number Diff line number Diff line
@@ -209,6 +209,7 @@ void spram_config(void) 
	case CPU_PROAPTIV:

	case CPU_P5600:

	case CPU_QEMU_GENERIC:

	case CPU_I6400:

		config0 = read_c0_config();

		/* FIXME: addresses are Malta specific */

		if (config0 & (1<<24)) {