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Commit 4e73238d authored by Wu Zhangjin's avatar Wu Zhangjin Committed by Ralf Baechle
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MIPS: Oprofile: Fix Loongson irq handler 


    
    The interrupt enable bit for the performance counters is in the Control
    Register $24, not in the counter register.
    loongson2_perfcount_handler(), we need to use
    
    Reported-by: default avatarXu Hengyang <hengyang@mail.ustc.edu.cn>
    Signed-off-by: default avatarWu Zhangjin <wuzhangjin@gmail.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: http://patchwork.linux-mips.org/patch/1198/


    Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>

---
parent 46afb829

arch/mips/oprofile/op_model_loongson2.c

+1 −1
Original line number Diff line number Diff line
@@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) 
	 */



	/* Check whether the irq belongs to me */

	enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;

	enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;

	if (!enabled)

		return IRQ_NONE;

	enabled = reg.cnt1_enabled | reg.cnt2_enabled;