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Commit 4ce001ab authored by Dave Airlie's avatar Dave Airlie
Browse files

drm/radeon/kms: add initial radeon tv-out support. 



This ports the tv-out code from the DDX to KMS.

adds a radeon.tv module option, radeon.tv=0 to disable tv

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 551ebd83

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \ 
	radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \

	radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \

	rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \

	radeon_test.o r200.o

	radeon_test.o r200.o radeon_legacy_tv.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

drivers/gpu/drm/radeon/atombios.h

+11 −0
Original line number Diff line number Diff line
@@ -2374,6 +2374,17 @@ typedef struct _ATOM_ANALOG_TV_INFO { 
	ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];

} ATOM_ANALOG_TV_INFO;



#define MAX_SUPPORTED_TV_TIMING_V1_2    3



typedef struct _ATOM_ANALOG_TV_INFO_V1_2 {

	ATOM_COMMON_TABLE_HEADER sHeader;

	UCHAR                    ucTV_SupportedStandard;

	UCHAR                    ucTV_BootUpDefaultStandard;

	UCHAR                    ucExt_TV_ASIC_ID;

	UCHAR                    ucExt_TV_ASIC_SlaveAddr;

	ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];

} ATOM_ANALOG_TV_INFO_V1_2;



/**************************************************************************/

/*  VRAM usage and their defintions */

drivers/gpu/drm/radeon/atombios_crtc.c

+72 −27
Original line number Diff line number Diff line
@@ -31,6 +31,10 @@ 
#include "atom.h"

#include "atom-bits.h"



/* evil but including atombios.h is much worse */

bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,

				SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,

				int32_t *pixel_clock);

static void atombios_overscan_setup(struct drm_crtc *crtc,

				    struct drm_display_mode *mode,

				    struct drm_display_mode *adjusted_mode)
@@ -89,17 +93,32 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

	ENABLE_SCALER_PS_ALLOCATION args;

	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);



	/* fixme - fill in enc_priv for atom dac */

	enum radeon_tv_std tv_std = TV_STD_NTSC;

	bool is_tv = false, is_cv = false;

	struct drm_encoder *encoder;



	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)

		return;



	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

		/* find tv std */

		if (encoder->crtc == crtc) {

			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {

				struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;

				tv_std = tv_dac->tv_std;

				is_tv = true;

			}

		}

	}



	memset(&args, 0, sizeof(args));



	args.ucScaler = radeon_crtc->crtc_id;



	if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) {

	if (is_tv) {

		switch (tv_std) {

		case TV_STD_NTSC:

		default:
@@ -128,7 +147,7 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) 
			break;

		}

		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;

	} else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) {

	} else if (is_cv) {

		args.ucTVStandard = ATOM_TV_CV;

		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;

	} else {
@@ -151,9 +170,9 @@ static void atombios_scaler_setup(struct drm_crtc *crtc) 
		}

	}

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

	if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)

	    && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) {

		atom_rv515_force_tv_scaler(rdev);

	if ((is_tv || is_cv)

	    && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {

		atom_rv515_force_tv_scaler(rdev, radeon_crtc);

	}

}
@@ -551,16 +570,41 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, 
	struct radeon_device *rdev = dev->dev_private;

	struct drm_encoder *encoder;

	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;

	int need_tv_timings = 0;

	bool ret;



	/* TODO color tiling */

	memset(&crtc_timing, 0, sizeof(crtc_timing));



	/* TODO tv */

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {



		/* find tv std */

		if (encoder->crtc == crtc) {

			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);



			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {

				struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;

				if (tv_dac) {

					if (tv_dac->tv_std == TV_STD_NTSC ||

					    tv_dac->tv_std == TV_STD_NTSC_J ||

					    tv_dac->tv_std == TV_STD_PAL_M)

						need_tv_timings = 1;

					else

						need_tv_timings = 2;

					break;

				}

			}

		}

	}



	crtc_timing.ucCRTC = radeon_crtc->crtc_id;

	if (need_tv_timings) {

		ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1,

						 &crtc_timing, &adjusted_mode->clock);

		if (ret == false)

			need_tv_timings = 0;

	}



	if (!need_tv_timings) {

		crtc_timing.usH_Total = adjusted_mode->crtc_htotal;

		crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;

		crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
@@ -587,6 +631,7 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, 


		if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)

			crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;

	}



	atombios_crtc_set_pll(crtc, adjusted_mode);

	atombios_crtc_set_timing(crtc, &crtc_timing);

drivers/gpu/drm/radeon/radeon.h

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ extern int radeon_gart_size; 
extern int radeon_benchmarking;

extern int radeon_testing;

extern int radeon_connector_table;

extern int radeon_tv;



/*

 * Copy from radeon_drv.h so we don't have to include both and have conflicting

drivers/gpu/drm/radeon/radeon_atombios.c

+68 −7
Original line number Diff line number Diff line
@@ -471,11 +471,6 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct 
			continue;

		}



		if (i == ATOM_DEVICE_TV1_INDEX) {

			DRM_DEBUG("Skipping TV Out\n");

			continue;

		}



		bios_connectors[i].connector_type =

		    supported_devices_connector_convert[ci.sucConnectorInfo.

							sbfAccess.
@@ -858,6 +853,72 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 
	return p_dac;

}



bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,

				SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,

				int32_t *pixel_clock)

{

	struct radeon_mode_info *mode_info = &rdev->mode_info;

	ATOM_ANALOG_TV_INFO *tv_info;

	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;

	ATOM_DTD_FORMAT *dtd_timings;

	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);

	u8 frev, crev;

	uint16_t data_offset;



	atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);



	switch (crev) {

	case 1:

		tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);

		if (index > MAX_SUPPORTED_TV_TIMING)

			return false;



		crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);

		crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);

		crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);

		crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);



		crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);

		crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);

		crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);

		crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);



		crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;



		crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);

		crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);

		crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);

		crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);

		*pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;



		if (index == 1) {

			/* PAL timings appear to have wrong values for totals */

			crtc_timing->usH_Total -= 1;

			crtc_timing->usV_Total -= 1;

		}

		break;

	case 2:

		tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);

		if (index > MAX_SUPPORTED_TV_TIMING_V1_2)

			return false;



		dtd_timings = &tv_info_v1_2->aModeTimings[index];

		crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);

		crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);

		crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);

		crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);

		crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);

		crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);

		crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);

		crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);



		crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);

		*pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;

		break;

	}

	return true;

}



struct radeon_encoder_tv_dac *

radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)

{
@@ -948,10 +1009,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 
	uint32_t bios_2_scratch, bios_6_scratch;



	if (rdev->family >= CHIP_R600) {

		bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH);

		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);

		bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);

	} else {

		bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH);

		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);

		bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);

	}