Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4be5097c authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: enable uvd bypass mode for CI/VI. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3f767e3d

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

+22 −3
Original line number Diff line number Diff line
@@ -36,6 +36,9 @@ 


#include "bif/bif_4_1_d.h"



#include "smu/smu_7_0_1_d.h"

#include "smu/smu_7_0_1_sh_mask.h"



static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);

static void uvd_v4_2_init_cg(struct amdgpu_device *adev);

static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
@@ -683,18 +686,34 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 
	return 0;

}



static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)

{

	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);



	if (enable)

		tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |

			GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);

	else

		tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |

			 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);



	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);

}



static int uvd_v4_2_set_clockgating_state(void *handle,

					  enum amd_clockgating_state state)

{

	bool gate = false;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))

		return 0;



	if (state == AMD_CG_STATE_GATE)

		gate = true;



	uvd_v5_0_set_bypass_mode(adev, gate);



	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))

		return 0;



	uvd_v4_2_enable_mgcg(adev, gate);



	return 0;

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

+18 −0
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ 
#include "oss/oss_2_0_sh_mask.h"

#include "bif/bif_5_0_d.h"

#include "vi.h"

#include "smu/smu_7_1_2_d.h"

#include "smu/smu_7_1_2_sh_mask.h"



static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);

static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -722,6 +724,20 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 
}

#endif



static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)

{

	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);



	if (enable)

		tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |

			GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);

	else

		tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |

			 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);



	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);

}



static int uvd_v5_0_set_clockgating_state(void *handle,

					  enum amd_clockgating_state state)

{
@@ -729,6 +745,8 @@ static int uvd_v5_0_set_clockgating_state(void *handle, 
	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;

	static int curstate = -1;



	uvd_v5_0_set_bypass_mode(adev, enable);



	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))

		return 0;

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

+4 −5
Original line number Diff line number Diff line
@@ -935,7 +935,7 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) 
}

#endif



static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable)

static void uvd_v6_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)

{

	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
@@ -953,15 +953,14 @@ static int uvd_v6_0_set_clockgating_state(void *handle, 
					  enum amd_clockgating_state state)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;



	if (adev->asic_type == CHIP_FIJI ||

	    adev->asic_type == CHIP_POLARIS10)

		uvd_v6_set_bypass_mode(adev, state == AMD_CG_STATE_GATE ? true : false);

	uvd_v6_0_set_bypass_mode(adev, enable);



	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))

		return 0;



	if (state == AMD_CG_STATE_GATE) {

	if (enable) {

		/* disable HW gating and enable Sw gating */

		uvd_v6_0_set_sw_clock_gating(adev);

	} else {