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Commit 4a1fd556 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
Browse files

[ARM] fix 48d7927b



The proc-*.S files have the _prefetch_abort pointer placed at the end
of the processor structure but the cpu-multi32.h defines it in the
second position. The patch also fixes the support for XSC3 and the
MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 328d8a01
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+6 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ config CPU_ARM7TDMI
	depends on !MMU
	select CPU_32v4T
	select CPU_ABRT_LV4T
	select CPU_PABRT_NOIFAR
	select CPU_CACHE_V4
	help
	  A 32-bit RISC microprocessor based on the ARM7 processor core
@@ -85,6 +86,7 @@ config CPU_ARM740T
	depends on !MMU
	select CPU_32v4T
	select CPU_ABRT_LV4T
	select CPU_PABRT_NOIFAR
	select CPU_CACHE_V3	# although the core is v4t
	select CPU_CP15_MPU
	help
@@ -101,6 +103,7 @@ config CPU_ARM9TDMI
	depends on !MMU
	select CPU_32v4T
	select CPU_ABRT_NOMMU
	select CPU_PABRT_NOIFAR
	select CPU_CACHE_V4
	help
	  A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -200,6 +203,7 @@ config CPU_ARM940T
	depends on !MMU
	select CPU_32v4T
	select CPU_ABRT_NOMMU
	select CPU_PABRT_NOIFAR
	select CPU_CACHE_VIVT
	select CPU_CP15_MPU
	help
@@ -217,6 +221,7 @@ config CPU_ARM946E
	depends on !MMU
	select CPU_32v5
	select CPU_ABRT_NOMMU
	select CPU_PABRT_NOIFAR
	select CPU_CACHE_VIVT
	select CPU_CP15_MPU
	help
@@ -351,6 +356,7 @@ config CPU_XSC3
	default y
	select CPU_32v5
	select CPU_ABRT_EV5T
	select CPU_PABRT_NOIFAR
	select CPU_CACHE_VIVT
	select CPU_CP15_MMU
	select CPU_TLB_V4WBI if MMU
+1 −1
Original line number Diff line number Diff line
@@ -471,6 +471,7 @@ arm1020_crval:
	.type	arm1020_processor_functions, #object
arm1020_processor_functions:
	.word	v4t_early_abort
	.word	pabort_noifar
	.word	cpu_arm1020_proc_init
	.word	cpu_arm1020_proc_fin
	.word	cpu_arm1020_reset
@@ -478,7 +479,6 @@ arm1020_processor_functions:
	.word	cpu_arm1020_dcache_clean_area
	.word	cpu_arm1020_switch_mm
	.word	cpu_arm1020_set_pte_ext
	.word	pabort_noifar
	.size	arm1020_processor_functions, . - arm1020_processor_functions

	.section ".rodata"
+1 −1
Original line number Diff line number Diff line
@@ -452,6 +452,7 @@ arm1020e_crval:
	.type	arm1020e_processor_functions, #object
arm1020e_processor_functions:
	.word	v4t_early_abort
	.word	pabort_noifar
	.word	cpu_arm1020e_proc_init
	.word	cpu_arm1020e_proc_fin
	.word	cpu_arm1020e_reset
@@ -459,7 +460,6 @@ arm1020e_processor_functions:
	.word	cpu_arm1020e_dcache_clean_area
	.word	cpu_arm1020e_switch_mm
	.word	cpu_arm1020e_set_pte_ext
	.word	pabort_noifar
	.size	arm1020e_processor_functions, . - arm1020e_processor_functions

	.section ".rodata"
+1 −1
Original line number Diff line number Diff line
@@ -435,6 +435,7 @@ arm1022_crval:
	.type	arm1022_processor_functions, #object
arm1022_processor_functions:
	.word	v4t_early_abort
	.word	pabort_noifar
	.word	cpu_arm1022_proc_init
	.word	cpu_arm1022_proc_fin
	.word	cpu_arm1022_reset
@@ -442,7 +443,6 @@ arm1022_processor_functions:
	.word	cpu_arm1022_dcache_clean_area
	.word	cpu_arm1022_switch_mm
	.word	cpu_arm1022_set_pte_ext
	.word	pabort_noifar
	.size	arm1022_processor_functions, . - arm1022_processor_functions

	.section ".rodata"
+1 −1
Original line number Diff line number Diff line
@@ -430,6 +430,7 @@ arm1026_crval:
	.type	arm1026_processor_functions, #object
arm1026_processor_functions:
	.word	v5t_early_abort
	.word	pabort_noifar
	.word	cpu_arm1026_proc_init
	.word	cpu_arm1026_proc_fin
	.word	cpu_arm1026_reset
@@ -437,7 +438,6 @@ arm1026_processor_functions:
	.word	cpu_arm1026_dcache_clean_area
	.word	cpu_arm1026_switch_mm
	.word	cpu_arm1026_set_pte_ext
	.word	pabort_noifar
	.size	arm1026_processor_functions, . - arm1026_processor_functions

	.section .rodata
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