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Commit 4a00680b authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Add Goldmont V8 event file 



Add a Intel event file for perf.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-q87xlo75ffonydbmvf6lr18n@git.kernel.org


[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 052aa3cc

tools/perf/pmu-events/arch/x86/goldmont/cache.json

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tools/perf/pmu-events/arch/x86/goldmont/frontend.json

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[

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).  The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",

        "EventCode": "0x80",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "ICACHE.HIT",

        "SampleAfterValue": "200003",

        "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture"

    },

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",

        "EventCode": "0x80",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "ICACHE.MISSES",

        "SampleAfterValue": "200003",

        "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture"

    },

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",

        "EventCode": "0x80",

        "Counter": "0,1,2,3",

        "UMask": "0x3",

        "EventName": "ICACHE.ACCESSES",

        "SampleAfterValue": "200003",

        "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture"

    },

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops.  The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",

        "EventCode": "0xE7",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "MS_DECODED.MS_ENTRY",

        "SampleAfterValue": "200003",

        "BriefDescription": "MS decode starts"

    },

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",

        "EventCode": "0xE9",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",

        "SampleAfterValue": "200003",

        "BriefDescription": "Decode restrictions due to predicting wrong instruction length"

    }

]
 
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tools/perf/pmu-events/arch/x86/goldmont/memory.json

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[

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.",

        "EventCode": "0xC3",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "SampleAfterValue": "200003",

        "BriefDescription": "Machine clears due to memory ordering issue"

    },

    {

        "PEBS": "2",

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.",

        "EventCode": "0x13",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",

        "SampleAfterValue": "200003",

        "BriefDescription": "Load uops that split a page (Precise event capable)"

    },

    {

        "PEBS": "2",

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.",

        "EventCode": "0x13",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",

        "SampleAfterValue": "200003",

        "BriefDescription": "Store uops that split a page (Precise event capable)"

    }

]
 
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tools/perf/pmu-events/arch/x86/goldmont/other.json

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[

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend.  Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable.   Note that uops must be available for consumption in order for this event to fire.  If a uop is not available (Instruction Queue is empty), this event will not count.",

        "EventCode": "0xCA",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",

        "SampleAfterValue": "200003",

        "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend"

    },

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows).   Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",

        "EventCode": "0xCA",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",

        "SampleAfterValue": "200003",

        "BriefDescription": "Unfilled issue slots per cycle to recover"

    },

    {

        "CollectPEBSRecord": "1",

        "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource  in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",

        "EventCode": "0xCA",

        "Counter": "0,1,2,3",

        "UMask": "0x0",

        "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",

        "SampleAfterValue": "200003",

        "BriefDescription": "Unfilled issue slots per cycle"

    },

    {

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts hardware interrupts received by the processor.",

        "EventCode": "0xCB",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "HW_INTERRUPTS.RECEIVED",

        "SampleAfterValue": "200003",

        "BriefDescription": "Hardware interrupts received (Precise event capable)"

    },

    {

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",

        "EventCode": "0xCB",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",

        "SampleAfterValue": "200003",

        "BriefDescription": "Cycles pending interrupts are masked (Precise event capable)"

    }

]
 
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tools/perf/pmu-events/arch/x86/goldmont/pipeline.json

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