Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 497e803e authored by Matt Redfearn's avatar Matt Redfearn Committed by Ralf Baechle
Browse files

MIPS: smp-cps: Ensure secondary cores start with EVA disabled 



The kernel currently assumes that a core will start up in legacy mode
using the exception base provided through the CM GCR registers. If a
core has been configured in hardware to start in EVA mode, these
assumptions will fail.

This patch ensures that secondary cores are initialized to meet these
assumptions.

Signed-off-by: default avatarMatt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11907/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a68f3768

arch/mips/include/asm/mips-cm.h

+4 −0
Original line number Diff line number Diff line
@@ -243,6 +243,10 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) 
#define  CM_GCR_BASE_CMDEFTGT_IOCU0		2

#define  CM_GCR_BASE_CMDEFTGT_IOCU1		3



/* GCR_RESET_EXT_BASE register fields */

#define CM_GCR_RESET_EXT_BASE_EVARESET		BIT(31)

#define CM_GCR_RESET_EXT_BASE_UEB		BIT(30)



/* GCR_ACCESS register fields */

#define CM_GCR_ACCESS_ACCESSEN_SHF		0

#define CM_GCR_ACCESS_ACCESSEN_MSK		(_ULCAST_(0xff) << 0)

arch/mips/kernel/smp-cps.c

+3 −0
Original line number Diff line number Diff line
@@ -202,6 +202,9 @@ static void boot_core(unsigned core) 
	/* Ensure its coherency is disabled */

	write_gcr_co_coherence(0);



	/* Start it with the legacy memory map and exception base */

	write_gcr_co_reset_ext_base(CM_GCR_RESET_EXT_BASE_UEB);



	/* Ensure the core can access the GCRs */

	access = read_gcr_access();

	access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);