Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 487bda54 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 

Pull arm64 fixes from Catalin Marinas:
 - correct argument type (pgprot_t) when calling __ioremap()
 - PCI_IOBASE virtual address change
 - use architected event for CPU cycle counter
 - fix ELF core dumping
 - select CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 - missing completion for secondary CPU boot
 - booting on systems with all memory beyond 4GB

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64:
  arm64: mm: fix booting on systems with no memory below 4GB
  arm64: smp: add missing completion for secondary boot
  arm64: compat: select CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION
  arm64: elf: fix core dumping definitions for GP and FP registers
  arm64: perf: use architected event for CPU cycle counter
  arm64: Move PCI_IOBASE closer to MODULES_VADDR
  arm64: Use pgprot_t as the last argument when invoking __ioremap()
parents 0020dd0b f483a853

Documentation/arm64/memory.txt

+6 −6
Original line number Diff line number Diff line
@@ -27,17 +27,17 @@ Start End Size Use 
-----------------------------------------------------------------------

0000000000000000	0000007fffffffff	 512GB		user



ffffff8000000000	ffffffbbfffcffff	~240GB		vmalloc

ffffff8000000000	ffffffbbfffeffff	~240GB		vmalloc



ffffffbbfffd0000	ffffffbcfffdffff	  64KB		[guard page]

ffffffbbffff0000	ffffffbbffffffff	  64KB		[guard page]



ffffffbbfffe0000	ffffffbcfffeffff	  64KB		PCI I/O space

ffffffbc00000000	ffffffbdffffffff	   8GB		vmemmap



ffffffbbffff0000	ffffffbcffffffff	  64KB		[guard page]

ffffffbe00000000	ffffffbffbbfffff	  ~8GB		[guard, future vmmemap]



ffffffbc00000000	ffffffbdffffffff	   8GB		vmemmap

ffffffbffbe00000	ffffffbffbe0ffff	  64KB		PCI I/O space



ffffffbe00000000	ffffffbffbffffff	  ~8GB		[guard, future vmmemap]

ffffffbbffff0000	ffffffbcffffffff	  ~2MB		[guard]



ffffffbffc000000	ffffffbfffffffff	  64MB		modules

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line 
config ARM64

	def_bool y

	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE

	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION

	select GENERIC_CLOCKEVENTS

	select GENERIC_HARDIRQS_NO_DEPRECATED

	select GENERIC_IOMAP

arch/arm64/include/asm/elf.h

+1 −4
Original line number Diff line number Diff line
@@ -25,12 +25,10 @@ 
#include <asm/user.h>



typedef unsigned long elf_greg_t;

typedef unsigned long elf_freg_t[3];



#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))

typedef elf_greg_t elf_gregset_t[ELF_NGREG];



typedef struct user_fp elf_fpregset_t;

typedef struct user_fpsimd_state elf_fpregset_t;



#define EM_AARCH64		183
@@ -87,7 +85,6 @@ typedef struct user_fp elf_fpregset_t; 
#define R_AARCH64_MOVW_PREL_G2_NC	292

#define R_AARCH64_MOVW_PREL_G3		293





/*

 * These are used to set parameters in the core dumps.

 */

arch/arm64/include/asm/fpsimd.h

+2 −3
Original line number Diff line number Diff line
@@ -25,9 +25,8 @@ 
 *  - FPSR and FPCR

 *  - 32 128-bit data registers

 *

 * Note that user_fp forms a prefix of this structure, which is relied

 * upon in the ptrace FP/SIMD accessors. struct user_fpsimd_state must

 * form a prefix of struct fpsimd_state.

 * Note that user_fpsimd forms a prefix of this structure, which is

 * relied upon in the ptrace FP/SIMD accessors.

 */

struct fpsimd_state {

	union {

arch/arm64/include/asm/io.h

+4 −4
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) 
 *  I/O port access primitives.

 */

#define IO_SPACE_LIMIT		0xffff

#define PCI_IOBASE		((void __iomem *)0xffffffbbfffe0000UL)

#define PCI_IOBASE		((void __iomem *)(MODULES_VADDR - SZ_2M))



static inline u8 inb(unsigned long addr)

{
@@ -225,9 +225,9 @@ extern void __iounmap(volatile void __iomem *addr); 
#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_XN | PTE_ATTRINDX(MT_DEVICE_nGnRE))

#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))



#define ioremap(addr, size)		__ioremap((addr), (size), PROT_DEVICE_nGnRE)

#define ioremap_nocache(addr, size)	__ioremap((addr), (size), PROT_DEVICE_nGnRE)

#define ioremap_wc(addr, size)		__ioremap((addr), (size), PROT_NORMAL_NC)

#define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))

#define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))

#define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))

#define iounmap				__iounmap



#define ARCH_HAS_IOREMAP_WC