Loading drivers/hwmon/pmbus/pmbus.h +26 −24 Original line number Diff line number Diff line Loading @@ -162,30 +162,32 @@ #define PMBUS_VIRT_READ_IIN_MAX (PMBUS_VIRT_BASE + 10) #define PMBUS_VIRT_RESET_IIN_HISTORY (PMBUS_VIRT_BASE + 11) #define PMBUS_VIRT_READ_PIN_AVG (PMBUS_VIRT_BASE + 12) #define PMBUS_VIRT_READ_PIN_MAX (PMBUS_VIRT_BASE + 13) #define PMBUS_VIRT_RESET_PIN_HISTORY (PMBUS_VIRT_BASE + 14) #define PMBUS_VIRT_READ_POUT_AVG (PMBUS_VIRT_BASE + 15) #define PMBUS_VIRT_READ_POUT_MAX (PMBUS_VIRT_BASE + 16) #define PMBUS_VIRT_RESET_POUT_HISTORY (PMBUS_VIRT_BASE + 17) #define PMBUS_VIRT_READ_VOUT_AVG (PMBUS_VIRT_BASE + 18) #define PMBUS_VIRT_READ_VOUT_MIN (PMBUS_VIRT_BASE + 19) #define PMBUS_VIRT_READ_VOUT_MAX (PMBUS_VIRT_BASE + 20) #define PMBUS_VIRT_RESET_VOUT_HISTORY (PMBUS_VIRT_BASE + 21) #define PMBUS_VIRT_READ_IOUT_AVG (PMBUS_VIRT_BASE + 22) #define PMBUS_VIRT_READ_IOUT_MIN (PMBUS_VIRT_BASE + 23) #define PMBUS_VIRT_READ_IOUT_MAX (PMBUS_VIRT_BASE + 24) #define PMBUS_VIRT_RESET_IOUT_HISTORY (PMBUS_VIRT_BASE + 25) #define PMBUS_VIRT_READ_TEMP2_AVG (PMBUS_VIRT_BASE + 26) #define PMBUS_VIRT_READ_TEMP2_MIN (PMBUS_VIRT_BASE + 27) #define PMBUS_VIRT_READ_TEMP2_MAX (PMBUS_VIRT_BASE + 28) #define PMBUS_VIRT_RESET_TEMP2_HISTORY (PMBUS_VIRT_BASE + 29) #define PMBUS_VIRT_READ_VMON (PMBUS_VIRT_BASE + 30) #define PMBUS_VIRT_VMON_UV_WARN_LIMIT (PMBUS_VIRT_BASE + 31) #define PMBUS_VIRT_VMON_OV_WARN_LIMIT (PMBUS_VIRT_BASE + 32) #define PMBUS_VIRT_VMON_UV_FAULT_LIMIT (PMBUS_VIRT_BASE + 33) #define PMBUS_VIRT_VMON_OV_FAULT_LIMIT (PMBUS_VIRT_BASE + 34) #define PMBUS_VIRT_STATUS_VMON (PMBUS_VIRT_BASE + 35) #define PMBUS_VIRT_READ_PIN_MIN (PMBUS_VIRT_BASE + 13) #define PMBUS_VIRT_READ_PIN_MAX (PMBUS_VIRT_BASE + 14) #define PMBUS_VIRT_RESET_PIN_HISTORY (PMBUS_VIRT_BASE + 15) #define PMBUS_VIRT_READ_POUT_AVG (PMBUS_VIRT_BASE + 16) #define PMBUS_VIRT_READ_POUT_MIN (PMBUS_VIRT_BASE + 17) #define PMBUS_VIRT_READ_POUT_MAX (PMBUS_VIRT_BASE + 18) #define PMBUS_VIRT_RESET_POUT_HISTORY (PMBUS_VIRT_BASE + 19) #define PMBUS_VIRT_READ_VOUT_AVG (PMBUS_VIRT_BASE + 20) #define PMBUS_VIRT_READ_VOUT_MIN (PMBUS_VIRT_BASE + 21) #define PMBUS_VIRT_READ_VOUT_MAX (PMBUS_VIRT_BASE + 22) #define PMBUS_VIRT_RESET_VOUT_HISTORY (PMBUS_VIRT_BASE + 23) #define PMBUS_VIRT_READ_IOUT_AVG (PMBUS_VIRT_BASE + 24) #define PMBUS_VIRT_READ_IOUT_MIN (PMBUS_VIRT_BASE + 25) #define PMBUS_VIRT_READ_IOUT_MAX (PMBUS_VIRT_BASE + 26) #define PMBUS_VIRT_RESET_IOUT_HISTORY (PMBUS_VIRT_BASE + 27) #define PMBUS_VIRT_READ_TEMP2_AVG (PMBUS_VIRT_BASE + 28) #define PMBUS_VIRT_READ_TEMP2_MIN (PMBUS_VIRT_BASE + 29) #define PMBUS_VIRT_READ_TEMP2_MAX (PMBUS_VIRT_BASE + 30) #define PMBUS_VIRT_RESET_TEMP2_HISTORY (PMBUS_VIRT_BASE + 31) #define PMBUS_VIRT_READ_VMON (PMBUS_VIRT_BASE + 32) #define PMBUS_VIRT_VMON_UV_WARN_LIMIT (PMBUS_VIRT_BASE + 33) #define PMBUS_VIRT_VMON_OV_WARN_LIMIT (PMBUS_VIRT_BASE + 34) #define PMBUS_VIRT_VMON_UV_FAULT_LIMIT (PMBUS_VIRT_BASE + 35) #define PMBUS_VIRT_VMON_OV_FAULT_LIMIT (PMBUS_VIRT_BASE + 36) #define PMBUS_VIRT_STATUS_VMON (PMBUS_VIRT_BASE + 37) /* * OPERATION Loading drivers/hwmon/pmbus/pmbus_core.c +8 −0 Original line number Diff line number Diff line Loading @@ -1328,6 +1328,10 @@ static const struct pmbus_limit_attr pin_limit_attrs[] = { .reg = PMBUS_VIRT_READ_PIN_AVG, .update = true, .attr = "average", }, { .reg = PMBUS_VIRT_READ_PIN_MIN, .update = true, .attr = "input_lowest", }, { .reg = PMBUS_VIRT_READ_PIN_MAX, .update = true, Loading Loading @@ -1358,6 +1362,10 @@ static const struct pmbus_limit_attr pout_limit_attrs[] = { .reg = PMBUS_VIRT_READ_POUT_AVG, .update = true, .attr = "average", }, { .reg = PMBUS_VIRT_READ_POUT_MIN, .update = true, .attr = "input_lowest", }, { .reg = PMBUS_VIRT_READ_POUT_MAX, .update = true, Loading Loading
drivers/hwmon/pmbus/pmbus.h +26 −24 Original line number Diff line number Diff line Loading @@ -162,30 +162,32 @@ #define PMBUS_VIRT_READ_IIN_MAX (PMBUS_VIRT_BASE + 10) #define PMBUS_VIRT_RESET_IIN_HISTORY (PMBUS_VIRT_BASE + 11) #define PMBUS_VIRT_READ_PIN_AVG (PMBUS_VIRT_BASE + 12) #define PMBUS_VIRT_READ_PIN_MAX (PMBUS_VIRT_BASE + 13) #define PMBUS_VIRT_RESET_PIN_HISTORY (PMBUS_VIRT_BASE + 14) #define PMBUS_VIRT_READ_POUT_AVG (PMBUS_VIRT_BASE + 15) #define PMBUS_VIRT_READ_POUT_MAX (PMBUS_VIRT_BASE + 16) #define PMBUS_VIRT_RESET_POUT_HISTORY (PMBUS_VIRT_BASE + 17) #define PMBUS_VIRT_READ_VOUT_AVG (PMBUS_VIRT_BASE + 18) #define PMBUS_VIRT_READ_VOUT_MIN (PMBUS_VIRT_BASE + 19) #define PMBUS_VIRT_READ_VOUT_MAX (PMBUS_VIRT_BASE + 20) #define PMBUS_VIRT_RESET_VOUT_HISTORY (PMBUS_VIRT_BASE + 21) #define PMBUS_VIRT_READ_IOUT_AVG (PMBUS_VIRT_BASE + 22) #define PMBUS_VIRT_READ_IOUT_MIN (PMBUS_VIRT_BASE + 23) #define PMBUS_VIRT_READ_IOUT_MAX (PMBUS_VIRT_BASE + 24) #define PMBUS_VIRT_RESET_IOUT_HISTORY (PMBUS_VIRT_BASE + 25) #define PMBUS_VIRT_READ_TEMP2_AVG (PMBUS_VIRT_BASE + 26) #define PMBUS_VIRT_READ_TEMP2_MIN (PMBUS_VIRT_BASE + 27) #define PMBUS_VIRT_READ_TEMP2_MAX (PMBUS_VIRT_BASE + 28) #define PMBUS_VIRT_RESET_TEMP2_HISTORY (PMBUS_VIRT_BASE + 29) #define PMBUS_VIRT_READ_VMON (PMBUS_VIRT_BASE + 30) #define PMBUS_VIRT_VMON_UV_WARN_LIMIT (PMBUS_VIRT_BASE + 31) #define PMBUS_VIRT_VMON_OV_WARN_LIMIT (PMBUS_VIRT_BASE + 32) #define PMBUS_VIRT_VMON_UV_FAULT_LIMIT (PMBUS_VIRT_BASE + 33) #define PMBUS_VIRT_VMON_OV_FAULT_LIMIT (PMBUS_VIRT_BASE + 34) #define PMBUS_VIRT_STATUS_VMON (PMBUS_VIRT_BASE + 35) #define PMBUS_VIRT_READ_PIN_MIN (PMBUS_VIRT_BASE + 13) #define PMBUS_VIRT_READ_PIN_MAX (PMBUS_VIRT_BASE + 14) #define PMBUS_VIRT_RESET_PIN_HISTORY (PMBUS_VIRT_BASE + 15) #define PMBUS_VIRT_READ_POUT_AVG (PMBUS_VIRT_BASE + 16) #define PMBUS_VIRT_READ_POUT_MIN (PMBUS_VIRT_BASE + 17) #define PMBUS_VIRT_READ_POUT_MAX (PMBUS_VIRT_BASE + 18) #define PMBUS_VIRT_RESET_POUT_HISTORY (PMBUS_VIRT_BASE + 19) #define PMBUS_VIRT_READ_VOUT_AVG (PMBUS_VIRT_BASE + 20) #define PMBUS_VIRT_READ_VOUT_MIN (PMBUS_VIRT_BASE + 21) #define PMBUS_VIRT_READ_VOUT_MAX (PMBUS_VIRT_BASE + 22) #define PMBUS_VIRT_RESET_VOUT_HISTORY (PMBUS_VIRT_BASE + 23) #define PMBUS_VIRT_READ_IOUT_AVG (PMBUS_VIRT_BASE + 24) #define PMBUS_VIRT_READ_IOUT_MIN (PMBUS_VIRT_BASE + 25) #define PMBUS_VIRT_READ_IOUT_MAX (PMBUS_VIRT_BASE + 26) #define PMBUS_VIRT_RESET_IOUT_HISTORY (PMBUS_VIRT_BASE + 27) #define PMBUS_VIRT_READ_TEMP2_AVG (PMBUS_VIRT_BASE + 28) #define PMBUS_VIRT_READ_TEMP2_MIN (PMBUS_VIRT_BASE + 29) #define PMBUS_VIRT_READ_TEMP2_MAX (PMBUS_VIRT_BASE + 30) #define PMBUS_VIRT_RESET_TEMP2_HISTORY (PMBUS_VIRT_BASE + 31) #define PMBUS_VIRT_READ_VMON (PMBUS_VIRT_BASE + 32) #define PMBUS_VIRT_VMON_UV_WARN_LIMIT (PMBUS_VIRT_BASE + 33) #define PMBUS_VIRT_VMON_OV_WARN_LIMIT (PMBUS_VIRT_BASE + 34) #define PMBUS_VIRT_VMON_UV_FAULT_LIMIT (PMBUS_VIRT_BASE + 35) #define PMBUS_VIRT_VMON_OV_FAULT_LIMIT (PMBUS_VIRT_BASE + 36) #define PMBUS_VIRT_STATUS_VMON (PMBUS_VIRT_BASE + 37) /* * OPERATION Loading
drivers/hwmon/pmbus/pmbus_core.c +8 −0 Original line number Diff line number Diff line Loading @@ -1328,6 +1328,10 @@ static const struct pmbus_limit_attr pin_limit_attrs[] = { .reg = PMBUS_VIRT_READ_PIN_AVG, .update = true, .attr = "average", }, { .reg = PMBUS_VIRT_READ_PIN_MIN, .update = true, .attr = "input_lowest", }, { .reg = PMBUS_VIRT_READ_PIN_MAX, .update = true, Loading Loading @@ -1358,6 +1362,10 @@ static const struct pmbus_limit_attr pout_limit_attrs[] = { .reg = PMBUS_VIRT_READ_POUT_AVG, .update = true, .attr = "average", }, { .reg = PMBUS_VIRT_READ_POUT_MIN, .update = true, .attr = "input_lowest", }, { .reg = PMBUS_VIRT_READ_POUT_MAX, .update = true, Loading