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Commit 4718a365 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+ 



All DDI platforms support the full set of preemph settings for each
supported vswing, so let's use the same code for them. We'll also move
the code into intel_ddi.c so that it sits closer to the actual buf trans
tables.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180517170309.28630-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent a393e964

drivers/gpu/drm/i915/intel_ddi.c

+20 −0
Original line number Diff line number Diff line
@@ -2115,6 +2115,26 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 
		DP_TRAIN_VOLTAGE_SWING_MASK;

}



/*

 * We assume that the full set of pre-emphasis values can be

 * used on all DDI platforms. Should that change we need to

 * rethink this code.

 */

u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)

{

	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {

	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:

		return DP_TRAIN_PRE_EMPH_LEVEL_3;

	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:

		return DP_TRAIN_PRE_EMPH_LEVEL_2;

	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:

		return DP_TRAIN_PRE_EMPH_LEVEL_1;

	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:

	default:

		return DP_TRAIN_PRE_EMPH_LEVEL_0;

	}

}



static void cnl_ddi_vswing_program(struct intel_encoder *encoder,

				   int level, enum intel_output_type type)

{

drivers/gpu/drm/i915/intel_dp.c

+4 −26
Original line number Diff line number Diff line
@@ -3239,33 +3239,11 @@ uint8_t 
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)

{

	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));

	enum port port = dp_to_dig_port(intel_dp)->base.port;

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	enum port port = encoder->port;



	if (INTEL_GEN(dev_priv) >= 9) {

		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:

			return DP_TRAIN_PRE_EMPH_LEVEL_3;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:

			return DP_TRAIN_PRE_EMPH_LEVEL_2;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:

			return DP_TRAIN_PRE_EMPH_LEVEL_1;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:

			return DP_TRAIN_PRE_EMPH_LEVEL_0;

		default:

			return DP_TRAIN_PRE_EMPH_LEVEL_0;

		}

	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:

			return DP_TRAIN_PRE_EMPH_LEVEL_3;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:

			return DP_TRAIN_PRE_EMPH_LEVEL_2;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:

			return DP_TRAIN_PRE_EMPH_LEVEL_1;

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:

		default:

			return DP_TRAIN_PRE_EMPH_LEVEL_0;

		}

	if (HAS_DDI(dev_priv)) {

		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {

		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -1410,6 +1410,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 
u32 bxt_signal_levels(struct intel_dp *intel_dp);

uint32_t ddi_signal_levels(struct intel_dp *intel_dp);

u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);

u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,

				 u8 voltage_swing);

int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,

				     bool enable);

void icl_map_plls_to_ports(struct drm_crtc *crtc,