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Commit 46d9cf52 authored by Biju Das's avatar Biju Das Committed by Simon Horman
Browse files

ARM: dts: r8a7743: Add internal PCI bridge nodes 



Add device nodes for the r8a7743 internal PCI bridge devices.

Signed-off-by: default avatarBiju Das <biju.das@bp.renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent d6ee8053

arch/arm/boot/dts/r8a7743.dtsi

+46 −0
Original line number Diff line number Diff line
@@ -821,6 +821,52 @@ 
			resets = <&cpg 311>;

			status = "disabled";

		};



		pci0: pci@ee090000 {

			compatible = "renesas,pci-r8a7743",

				     "renesas,pci-rcar-gen2";

			device_type = "pci";

			reg = <0 0xee090000 0 0xc00>,

			      <0 0xee080000 0 0x1100>;

			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 703>;

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 703>;

			status = "disabled";



			bus-range = <0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;

			interrupt-map-mask = <0xff00 0 0 0x7>;

			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH

					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH

					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

		};



		pci1: pci@ee0d0000 {

			compatible = "renesas,pci-r8a7743",

				     "renesas,pci-rcar-gen2";

			device_type = "pci";

			reg = <0 0xee0d0000 0 0xc00>,

			      <0 0xee0c0000 0 0x1100>;

			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 703>;

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 703>;

			status = "disabled";



			bus-range = <1 1>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;

			interrupt-map-mask = <0xff00 0 0 0x7>;

			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH

					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH

					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

		};

	};



	/* External root clock */