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Commit 4663f6ef authored by Bernd Schmidt's avatar Bernd Schmidt Committed by Mike Frysinger
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Blackfin: add ICPLB coverage for async banks 



When doing XIP, we need to execute out of the async banks, so we need
ICPLBs to allow this.

Signed-off-by: default avatarBernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 4a3e53c1

arch/blackfin/kernel/cplb-nompu/cplbinit.c

+9 −2
Original line number Original line Diff line number Diff line
@@ -36,7 +36,7 @@ int first_switched_icplb PDT_ATTR; 
int first_switched_dcplb PDT_ATTR;

int first_switched_dcplb PDT_ATTR;





struct cplb_boundary dcplb_bounds[9] PDT_ATTR;

struct cplb_boundary dcplb_bounds[9] PDT_ATTR;

struct cplb_boundary icplb_bounds[7] PDT_ATTR;

struct cplb_boundary icplb_bounds[9] PDT_ATTR;





int icplb_nr_bounds PDT_ATTR;

int icplb_nr_bounds PDT_ATTR;

int dcplb_nr_bounds PDT_ATTR;

int dcplb_nr_bounds PDT_ATTR;
@@ -167,14 +167,21 @@ void __init generate_cplb_tables_all(void) 
		icplb_bounds[i_i++].data = (reserved_mem_icache_on ?

		icplb_bounds[i_i++].data = (reserved_mem_icache_on ?

					    SDRAM_IGENERIC : SDRAM_INON_CHBL);

					    SDRAM_IGENERIC : SDRAM_INON_CHBL);

	}

	}

	/* Addressing hole up to the async bank.  */

	icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;

	icplb_bounds[i_i++].data = 0;

	/* ASYNC banks.  */

	icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;

	icplb_bounds[i_i++].data = SDRAM_EBIU;

	/* Addressing hole up to BootROM.  */

	/* Addressing hole up to BootROM.  */

	icplb_bounds[i_i].eaddr = BOOT_ROM_START;

	icplb_bounds[i_i].eaddr = BOOT_ROM_START;

	icplb_bounds[i_i++].data = 0;

	icplb_bounds[i_i++].data = 0;

	/* BootROM -- largest one should be less than 1 meg.  */

	/* BootROM -- largest one should be less than 1 meg.  */

	icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);

	icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);

	icplb_bounds[i_i++].data = SDRAM_IGENERIC;

	icplb_bounds[i_i++].data = SDRAM_IGENERIC;



	if (L2_LENGTH) {

	if (L2_LENGTH) {

		/* Addressing hole up to L2 SRAM, including the async bank.  */

		/* Addressing hole up to L2 SRAM.  */

		icplb_bounds[i_i].eaddr = L2_START;

		icplb_bounds[i_i].eaddr = L2_START;

		icplb_bounds[i_i++].data = 0;

		icplb_bounds[i_i++].data = 0;

		/* L2 SRAM.  */

		/* L2 SRAM.  */