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Commit 4586e4ea authored by Thor Thayer's avatar Thor Thayer Committed by Dinh Nguyen
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ARM: dts: Move Arria10 SDRAM as child of ECC Manager 



Changes to support ECC Manager as SDRAM IRQ parent by
1) updating IRQ property values to correct child IRQs
2) moving node under ECC Manager.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent a034a8d9

arch/arm/boot/dts/socfpga_arria10.dtsi

+7 −6
Original line number Original line Diff line number Diff line
@@ -572,12 +572,6 @@ 
			reg = <0xffcfb100 0x80>;

			reg = <0xffcfb100 0x80>;

		};

		};





		sdramedac {

			compatible = "altr,sdram-edac-a10";

			altr,sdr-syscon = <&sdr>;

			interrupts = <0 2 4>, <0 0 4>;

		};



		L2: l2-cache@fffff000 {

		L2: l2-cache@fffff000 {

			compatible = "arm,pl310-cache";

			compatible = "arm,pl310-cache";

			reg = <0xfffff000 0x1000>;

			reg = <0xfffff000 0x1000>;
@@ -614,6 +608,13 @@ 
			#interrupt-cells = <2>;

			#interrupt-cells = <2>;

			ranges;

			ranges;





			sdramedac {

				compatible = "altr,sdram-edac-a10";

				altr,sdr-syscon = <&sdr>;

				interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,

					     <49 IRQ_TYPE_LEVEL_HIGH>;

			};



			l2-ecc@ffd06010 {

			l2-ecc@ffd06010 {

				compatible = "altr,socfpga-a10-l2-ecc";

				compatible = "altr,socfpga-a10-l2-ecc";

				reg = <0xffd06010 0x4>;

				reg = <0xffd06010 0x4>;