Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4585945b authored by Philipp Zabel's avatar Philipp Zabel
Browse files

clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output 



The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 06445994

drivers/clk/mediatek/clk-mt8173.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -1095,6 +1095,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node) 
		clk_data->clks[cku->id] = clk;

		clk_data->clks[cku->id] = clk;

	}

	}





	clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,

				   base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,

				   NULL);

	clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;



	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

		pr_err("%s(): could not register clock provider: %d\n",

include/dt-bindings/clock/mt8173-clk.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -176,7 +176,8 @@ 
#define CLK_APMIXED_LVDSPLL		13

#define CLK_APMIXED_LVDSPLL		13

#define CLK_APMIXED_MSDCPLL2		14

#define CLK_APMIXED_MSDCPLL2		14

#define CLK_APMIXED_REF2USB_TX		15

#define CLK_APMIXED_REF2USB_TX		15

#define CLK_APMIXED_NR_CLK		16

#define CLK_APMIXED_HDMI_REF		16

#define CLK_APMIXED_NR_CLK		17





/* INFRA_SYS */

/* INFRA_SYS */