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Commit 44595982 authored by Paul Walmsley's avatar Paul Walmsley Committed by Tony Lindgren
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ARM: OMAP2: Change 24xx to use new register access 



This patch changes 24xx to use new register access, except for clock
framework. Clock framework register access will get updates in the
next patch.

Note that board-*.c files change GPMC (General Purpose Memory Controller)
access to use gpmc_cs_write_reg() instead of accessing the registers
directly. The code also uses gpmc_fck instead of it's parent clock
core_l3_ck for GPMC clock.

The H4 board file also adds h4_init_flash() function, which specify the
flash start and end addresses.

Also note that sleep.S removes some unused registers addresses.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent c595713d

arch/arm/mach-omap2/board-2430sdp.c

+14 −9
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 
#include <asm/arch/board.h>

#include <asm/arch/common.h>

#include <asm/arch/gpmc.h>

#include "prcm-regs.h"



#include <asm/io.h>
@@ -125,15 +124,18 @@ static inline void __init sdp2430_init_smc91x(void) 
	int eth_cs;

	unsigned long cs_mem_base;

	unsigned int rate;

	struct clk *l3ck;

	struct clk *gpmc_fck;



	eth_cs = SDP2430_SMC91X_CS;



	l3ck = clk_get(NULL, "core_l3_ck");

	if (IS_ERR(l3ck))

		rate = 100000000;

	else

		rate = clk_get_rate(l3ck);

	gpmc_fck = clk_get(NULL, "gpmc_fck");	/* Always on ENABLE_ON_INIT */

	if (IS_ERR(gpmc_fck)) {

		WARN_ON(1);

		return;

	}



	clk_enable(gpmc_fck);

	rate = clk_get_rate(gpmc_fck);



	/* Make sure CS1 timings are correct, for 2430 always muxed */

	gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
@@ -160,7 +162,7 @@ static inline void __init sdp2430_init_smc91x(void) 


	if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {

		printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");

		return;

		goto out;

	}



	sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
@@ -171,10 +173,13 @@ static inline void __init sdp2430_init_smc91x(void) 
		printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",

			OMAP24XX_ETHR_GPIO_IRQ);

		gpmc_cs_free(eth_cs);

		return;

		goto out;

	}

	omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);



out:

	clk_disable(gpmc_fck);

	clk_put(gpmc_fck);

}



static void __init omap_2430sdp_init_irq(void)

arch/arm/mach-omap2/board-apollon.c

+50 −10
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ 
#include <linux/interrupt.h>

#include <linux/delay.h>

#include <linux/leds.h>

#include <linux/err.h>

#include <linux/clk.h>



#include <asm/hardware.h>

#include <asm/mach-types.h>
@@ -39,7 +41,7 @@ 
#include <asm/arch/board.h>

#include <asm/arch/common.h>

#include <asm/arch/gpmc.h>

#include "prcm-regs.h"

#include <asm/arch/control.h>



/* LED & Switch macros */

#define LED0_GPIO13		13
@@ -187,17 +189,47 @@ static inline void __init apollon_init_smc91x(void) 
{

	unsigned long base;



	unsigned int rate;

	struct clk *gpmc_fck;

	int eth_cs;



	gpmc_fck = clk_get(NULL, "gpmc_fck");	/* Always on ENABLE_ON_INIT */

	if (IS_ERR(gpmc_fck)) {

		WARN_ON(1);

		return;

	}



	clk_enable(gpmc_fck);

	rate = clk_get_rate(gpmc_fck);



	eth_cs = APOLLON_ETH_CS;



	/* Make sure CS1 timings are correct */

	GPMC_CONFIG1_1 = 0x00011203;

	GPMC_CONFIG2_1 = 0x001f1f01;

	GPMC_CONFIG3_1 = 0x00080803;

	GPMC_CONFIG4_1 = 0x1c091c09;

	GPMC_CONFIG5_1 = 0x041f1f1f;

	GPMC_CONFIG6_1 = 0x000004c4;

	gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);



	if (rate >= 160000000) {

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);

	} else if (rate >= 130000000) {

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);

	} else {/* rate = 100000000 */

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);

	}



	if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {

		printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");

		return;

		goto out;

	}

	apollon_smc91x_resources[0].start = base + 0x300;

	apollon_smc91x_resources[0].end   = base + 0x30f;
@@ -208,9 +240,13 @@ static inline void __init apollon_init_smc91x(void) 
		printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",

			APOLLON_ETHR_GPIO_IRQ);

		gpmc_cs_free(APOLLON_ETH_CS);

		return;

		goto out;

	}

	omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);



out:

	clk_disable(gpmc_fck);

	clk_put(gpmc_fck);

}



static void __init omap_apollon_init_irq(void)
@@ -330,6 +366,8 @@ static void __init apollon_usb_init(void) 


static void __init omap_apollon_init(void)

{

	u32 v;



	apollon_led_init();

	apollon_sw_init();

	apollon_flash_init();
@@ -339,7 +377,9 @@ static void __init omap_apollon_init(void) 
	omap_cfg_reg(W19_24XX_SYS_NIRQ);



	/* Use Interal loop-back in MMC/SDIO Module Input Clock selection */

	CONTROL_DEVCONF |= (1 << 24);

	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);

	v |= (1 << 24);

	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);



	/*

 	 * Make sure the serial ports are muxed on at this point.

arch/arm/mach-omap2/board-h4.c

+101 −10
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ 
#include <linux/delay.h>

#include <linux/workqueue.h>

#include <linux/input.h>

#include <linux/err.h>

#include <linux/clk.h>



#include <asm/hardware.h>

#include <asm/mach-types.h>
@@ -26,6 +28,7 @@ 
#include <asm/mach/map.h>

#include <asm/mach/flash.h>



#include <asm/arch/control.h>

#include <asm/arch/gpio.h>

#include <asm/arch/gpioexpander.h>

#include <asm/arch/mux.h>
@@ -36,10 +39,13 @@ 
#include <asm/arch/keypad.h>

#include <asm/arch/menelaus.h>

#include <asm/arch/dma.h>

#include "prcm-regs.h"

#include <asm/arch/gpmc.h>



#include <asm/io.h>



#define H4_FLASH_CS	0

#define H4_SMC91X_CS	1



static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };

static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
@@ -116,8 +122,6 @@ static struct flash_platform_data h4_flash_data = { 
};



static struct resource h4_flash_resource = {

	.start		= H4_CS0_BASE,

	.end		= H4_CS0_BASE + SZ_64M - 1,

	.flags		= IORESOURCE_MEM,

};
@@ -253,21 +257,107 @@ static struct platform_device *h4_devices[] __initdata = { 
	&h4_lcd_device,

};



/* 2420 Sysboot setup (2430 is different) */

static u32 get_sysboot_value(void)

{

	return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &

		(OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |

		 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |

		 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));

}



/* H4-2420's always used muxed mode, H4-2422's always use non-muxed

 *

 * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423

 *  correctly.  The macro needs to look at production_id not just hawkeye.

 */

static u32 is_gpmc_muxed(void)

{

	u32 mux;

	mux = get_sysboot_value();

	if ((mux & 0xF) == 0xd)

		return 1;	/* NAND config (could be either) */

	if (mux & 0x2)		/* if mux'ed */

		return 1;

	else

		return 0;

}



static inline void __init h4_init_debug(void)

{

	int eth_cs;

	unsigned long cs_mem_base;

	unsigned int muxed, rate;

	struct clk *gpmc_fck;



	eth_cs	= H4_SMC91X_CS;



	gpmc_fck = clk_get(NULL, "gpmc_fck");	/* Always on ENABLE_ON_INIT */

	if (IS_ERR(gpmc_fck)) {

		WARN_ON(1);

		return;

	}



	clk_enable(gpmc_fck);

	rate = clk_get_rate(gpmc_fck);

	clk_disable(gpmc_fck);

	clk_put(gpmc_fck);



	if (is_gpmc_muxed())

		muxed = 0x200;

	else

		muxed = 0;



	/* Make sure CS1 timings are correct */

	GPMC_CONFIG1_1 = 0x00011200;

	GPMC_CONFIG2_1 = 0x001f1f01;

	GPMC_CONFIG3_1 = 0x00080803;

	GPMC_CONFIG4_1 = 0x1c091c09;

	GPMC_CONFIG5_1 = 0x041f1f1f;

	GPMC_CONFIG6_1 = 0x000004c4;

	GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);

	gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,

			  0x00011000 | muxed);



	if (rate >= 160000000) {

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);

	} else if (rate >= 130000000) {

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);

	} else {/* rate = 100000000 */

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);

		gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);

	}



	if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {

		printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");

		goto out;

	}



	udelay(100);



	omap_cfg_reg(M15_24XX_GPIO92);

	if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0)

		gpmc_cs_free(eth_cs);



out:

	clk_disable(gpmc_fck);

	clk_put(gpmc_fck);

}



static void __init h4_init_flash(void)

{

	unsigned long base;



	if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {

		printk("Can't request GPMC CS for flash\n");

		return;

	}

	h4_flash_resource.start	= base;

	h4_flash_resource.end	= base + SZ_64M - 1;

}



static void __init omap_h4_init_irq(void)
@@ -275,6 +365,7 @@ static void __init omap_h4_init_irq(void) 
	omap2_init_common_hw();

	omap_init_irq();

	omap_gpio_init();

	h4_init_flash();

}



static struct omap_uart_config h4_uart_config __initdata = {

arch/arm/mach-omap2/gpmc.c

+7 −5
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ static void __iomem *gpmc_base = 
static void __iomem *gpmc_cs_base =

	(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;



static struct clk *gpmc_l3_clk;

static struct clk *gpmc_fck;



static void gpmc_write_reg(int idx, u32 val)

{
@@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx) 
	return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);

}



/* TODO: Add support for gpmc_fck to clock framework and use it */

unsigned long gpmc_get_fclk_period(void)

{

	/* In picoseconds */

	return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);

	return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);

}



unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -398,8 +397,11 @@ void __init gpmc_init(void) 
{

	u32 l;



	gpmc_l3_clk = clk_get(NULL, "core_l3_ck");

	BUG_ON(IS_ERR(gpmc_l3_clk));

	gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */

	if (IS_ERR(gpmc_fck))

		WARN_ON(1);

	else

		clk_enable(gpmc_fck);



	l = gpmc_read_reg(GPMC_REVISION);

	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

arch/arm/mach-omap2/memory.c

+15 −11
Original line number Diff line number Diff line
@@ -27,11 +27,16 @@ 
#include <asm/arch/clock.h>

#include <asm/arch/sram.h>



#include "prcm-regs.h"

#include "prm.h"



#include "memory.h"

#include "sdrc.h"



unsigned long omap2_sdrc_base;

unsigned long omap2_sms_base;



static struct memory_timings mem_timings;

static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;



u32 omap2_memory_get_slow_dll_ctrl(void)

{
@@ -53,7 +58,7 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 
	unsigned long dll_cnt;

	u32 fast_dll = 0;



	mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */

	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */



	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.

	 * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -73,11 +78,11 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 
		mem_timings.dll_mode = M_LOCK;



	if (mem_timings.base_cs == 0) {

		fast_dll = SDRC_DLLA_CTRL;

		dll_cnt = SDRC_DLLA_STATUS & 0xff00;

		fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);

		dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;

	} else {

		fast_dll = SDRC_DLLB_CTRL;

		dll_cnt = SDRC_DLLB_STATUS & 0xff00;

		fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);

		dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;

	}

	if (force_lock_to_unlock_mode) {

		fast_dll &= ~0xff00;
@@ -106,14 +111,13 @@ void __init omap2_init_memory(void) 
{

	u32 l;



	l = SMS_SYSCONFIG;

	l = sms_read_reg(SMS_SYSCONFIG);

	l &= ~(0x3 << 3);

	l |= (0x2 << 3);

	SMS_SYSCONFIG = l;

	sms_write_reg(l, SMS_SYSCONFIG);



	l = SDRC_SYSCONFIG;

	l = sdrc_read_reg(SDRC_SYSCONFIG);

	l &= ~(0x3 << 3);

	l |= (0x2 << 3);

	SDRC_SYSCONFIG = l;



	sdrc_write_reg(l, SDRC_SYSCONFIG);

}