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Commit 44275932 authored by Radim Krčmář's avatar Radim Krčmář Committed by Paolo Bonzini
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KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch 



Our routines look at tscdeadline and period when deciding state of a
timer.  The timer is disarmed when switching between TSC deadline and
other modes, so we should set everything to disarmed state.

Signed-off-by: default avatarRadim Krčmář <rkrcmar@redhat.com>
Reviewed-by: default avatarWanpeng Li <wanpeng.li@hotmail.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 5d74a699

arch/x86/kvm/lapic.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -1330,8 +1330,10 @@ static void apic_update_lvtt(struct kvm_lapic *apic) 
	if (apic->lapic_timer.timer_mode != timer_mode) {

	if (apic->lapic_timer.timer_mode != timer_mode) {

		if (apic_lvtt_tscdeadline(apic) != (timer_mode ==

		if (apic_lvtt_tscdeadline(apic) != (timer_mode ==

				APIC_LVT_TIMER_TSCDEADLINE)) {

				APIC_LVT_TIMER_TSCDEADLINE)) {

			kvm_lapic_set_reg(apic, APIC_TMICT, 0);

			hrtimer_cancel(&apic->lapic_timer.timer);

			hrtimer_cancel(&apic->lapic_timer.timer);

			kvm_lapic_set_reg(apic, APIC_TMICT, 0);

			apic->lapic_timer.period = 0;

			apic->lapic_timer.tscdeadline = 0;

		}

		}

		apic->lapic_timer.timer_mode = timer_mode;

		apic->lapic_timer.timer_mode = timer_mode;

		limit_periodic_timer_frequency(apic);

		limit_periodic_timer_frequency(apic);