Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 42dc2a30 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Ingo Molnar:
 - misc fixes all around the map
 - block non-root vm86(old) if mmap_min_addr != 0
 - two small debuggability improvements
 - removal of obsolete paravirt op

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/platform: Fix Geode LX timekeeping in the generic x86 build
  x86/apic: Serialize LVTT and TSC_DEADLINE writes
  x86/ioapic: Force affinity setting in setup_ioapic_dest()
  x86/paravirt: Remove the unused pv_time_ops::get_tsc_khz method
  x86/ldt: Fix small LDT allocation for Xen
  x86/vm86: Fix the misleading CONFIG_VM86 Kconfig help text
  x86/cpu: Print family/model/stepping in hex
  x86/vm86: Block non-root vm86(old) if mmap_min_addr != 0
  x86/alternatives: Make optimize_nops() interrupt safe and synced
  x86/mm/srat: Print non-volatile flag in SRAT
  x86/cpufeatures: Enable cpuid for Intel SHA extensions
parents 1345df21 03da3ff1

arch/x86/Kconfig

+12 −11
Original line number Diff line number Diff line
@@ -1006,7 +1006,7 @@ config X86_THERMAL_VECTOR 
	depends on X86_MCE_INTEL



config X86_LEGACY_VM86

	bool "Legacy VM86 support (obsolete)"

	bool "Legacy VM86 support"

	default n

	depends on X86_32

	---help---
@@ -1018,19 +1018,20 @@ config X86_LEGACY_VM86 
	  available to accelerate real mode DOS programs.  However, any

	  recent version of DOSEMU, X, or vbetool should be fully

	  functional even without kernel VM86 support, as they will all

	  fall back to (pretty well performing) software emulation.

	  fall back to software emulation. Nevertheless, if you are using

	  a 16-bit DOS program where 16-bit performance matters, vm86

	  mode might be faster than emulation and you might want to

	  enable this option.



	  Anything that works on a 64-bit kernel is unlikely to need

	  this option, as 64-bit kernels don't, and can't, support V8086

	  mode.  This option is also unrelated to 16-bit protected mode

	  and is not needed to run most 16-bit programs under Wine.

	  Note that any app that works on a 64-bit kernel is unlikely to

	  need this option, as 64-bit kernels don't, and can't, support

	  V8086 mode. This option is also unrelated to 16-bit protected

	  mode and is not needed to run most 16-bit programs under Wine.



	  Enabling this option adds considerable attack surface to the

	  kernel and slows down system calls and exception handling.

	  Enabling this option increases the complexity of the kernel

	  and slows down exception handling a tiny bit.



	  Unless you use very old userspace or need the last drop of

	  performance in your real mode DOS games and can't use KVM,

	  say N here.

	  If unsure, say N here.



config VM86

       bool

arch/x86/include/asm/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ 
#define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */

#define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */

#define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */

#define X86_FEATURE_SHA_NI	( 9*32+29) /* SHA1/SHA256 Instruction Extensions */



/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */

#define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */

arch/x86/include/asm/paravirt_types.h

+0 −1
Original line number Diff line number Diff line
@@ -97,7 +97,6 @@ struct pv_lazy_ops { 
struct pv_time_ops {

	unsigned long long (*sched_clock)(void);

	unsigned long long (*steal_clock)(int cpu);

	unsigned long (*get_tsc_khz)(void);

};



struct pv_cpu_ops {

arch/x86/kernel/alternative.c

+5 −0
Original line number Diff line number Diff line
@@ -338,10 +338,15 @@ recompute_jump(struct alt_instr *a, u8 *orig_insn, u8 *repl_insn, u8 *insnbuf) 


static void __init_or_module optimize_nops(struct alt_instr *a, u8 *instr)

{

	unsigned long flags;



	if (instr[0] != 0x90)

		return;



	local_irq_save(flags);

	add_nops(instr + (a->instrlen - a->padlen), a->padlen);

	sync_core();

	local_irq_restore(flags);



	DUMP_BYTES(instr, a->instrlen, "%p: [%d:%d) optimized NOPs: ",

		   instr, a->instrlen - a->padlen, a->padlen);

arch/x86/kernel/apic/apic.c

+7 −0
Original line number Diff line number Diff line
@@ -336,6 +336,13 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 
	apic_write(APIC_LVTT, lvtt_value);



	if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {

		/*

		 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,

		 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.

		 * According to Intel, MFENCE can do the serialization here.

		 */

		asm volatile("mfence" : : : "memory");



		printk_once(KERN_DEBUG "TSC deadline timer enabled\n");

		return;

	}