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Commit 4217ff35 authored by Boris Brezillon's avatar Boris Brezillon
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Merge branch 'for-v4.7/gpmc-mtd-common' of github.com:rogerq/linux into nand/next 

Pull NAND/GPMC updates from Roger Quadros:
 "We do a couple of things in this series which result in cleaner device
  tree implementation, faster perfomance and multi-platform support. As
  an added bonus we get to use the GPMC_WAIT pins as GPI/Interrupts.

  - Establish a custom interface between NAND and GPMC driver. This is
    needed because all of the NAND registers sit in the GPMC register
    space.

  - Clean up device tree support so that omap-gpmc IP and the omap2 NAND
    driver can be used on non-OMAP platforms. e.g. Keystone.

  - Implement GPIOCHIP for the GPMC WAITPINS. SoCs can contain 2 to 4 of
    these and most of them would be unused otherwise. It also allows a
    cleaner implementation of NAND Ready pin status for the NAND driver.

  - Implement GPMC IRQ domain to proivde the 2 NAND events and GPMC
    WAITPIN edge interrupts.

  - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver.
    On dra7-evm, Read speed increases from 13768 KiB/ to 17246 KiB/s.
    Write speed was unchanged at 7123 KiB/s."

* 'for-v4.7/gpmc-mtd-common' of github.com:rogerq/linux:
  mtd: nand: omap2: Implement NAND ready using gpiolib
  memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via gpmc_regs
  memory: omap-gpmc: Support WAIT pin edge interrupts
  memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring
  memory: omap-gpmc: Support general purpose input for WAITPINs
  memory: omap-gpmc: Move device tree binding to correct location
  memory: omap-gpmc: Prevent mapping into 1st 16MB
  mtd: nand: omap: Update DT binding documentation
  mtd: nand: omap: Clean up device tree support
  mtd: nand: omap: Copy platform data parameters to omap_nand_info data
  mtd: nand: omap: Switch to using GPMC-NAND ops for writebuffer empty check
  mtd: nand: omap: Use gpmc_omap_get_nand_ops() to get NAND registers
  memory: omap-gpmc: Implement IRQ domain for NAND IRQs
  memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status
  memory: omap-gpmc: Introduce GPMC to NAND interface
  ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data
  ARM: OMAP2+: gpmc: Add platform data
parents f55532a0 10f22ee3

Documentation/devicetree/bindings/bus/ti-gpmc.txt→Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

+17 −0
Original line number Diff line number Diff line
@@ -32,6 +32,19 @@ Required properties: 
			bootloader) are used for the physical address decoding.

			As this will change in the future, filling correct

			values here is a requirement.

 - interrupt-controller: The GPMC driver implements and interrupt controller for

			the NAND events "fifoevent" and "termcount" plus the

			rising/falling edges on the GPMC_WAIT pins.

			The interrupt number mapping is as follows

			0 - NAND_fifoevent

			1 - NAND_termcount

			2 - GPMC_WAIT0 pin edge

			3 - GPMC_WAIT1 pin edge, and so on.

 - interrupt-cells:	Must be set to 2

 - gpio-controller:	The GPMC driver implements a GPIO controller for the

			GPMC WAIT pins that can be used as general purpose inputs.

			0 maps to GPMC_WAIT0 pin.

 - gpio-cells:		Must be set to 2



Timing properties for child nodes. All are optional and default to 0.
@@ -130,6 +143,10 @@ Example for an AM33xx board: 
		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */

		interrupt-controller;

		#interrupt-cells = <2>;

		gpio-controller;

		#gpio-cells = <2>;



		/* child nodes go here */

	};

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

+15 −4
Original line number Diff line number Diff line
@@ -13,7 +13,11 @@ Documentation/devicetree/bindings/mtd/nand.txt 


Required properties:



 - reg:		The CS line the peripheral is connected to

 - compatible:	"ti,omap2-nand"

 - reg:		range id (CS number), base offset and length of the

		NAND I/O space

 - interrupt-parent: must point to gpmc node

 - interrupts:	Two interrupt specifiers, one for fifoevent, one for termcount.



Optional properties:
@@ -44,6 +48,7 @@ Optional properties: 
		locating ECC errors for BCHx algorithms. SoC devices which have

		ELM hardware engines should specify this device node in .dtsi

		Using ELM for ECC error correction frees some CPU cycles.

 - rb-gpios:	GPIO specifier for the ready/busy# pin.



For inline partition table parsing (optional):
@@ -55,20 +60,26 @@ Example for an AM33xx board: 
	gpmc: gpmc@50000000 {

		compatible = "ti,am3352-gpmc";

		ti,hwmods = "gpmc";

		reg = <0x50000000 0x1000000>;

		reg = <0x50000000 0x36c>;

		interrupts = <100>;

		gpmc,num-cs = <8>;

		gpmc,num-waitpins = <2>;

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x08000000 0x2000>;	/* CS0: NAND */

		ranges = <0 0 0x08000000 0x1000000>;	/* CS0 space, 16MB */

		elm_id = <&elm>;

		interrupt-controller;

		#interrupt-cells = <2>;



		nand@0,0 {

			reg = <0 0 0>; /* CS0, offset 0 */

			compatible = "ti,omap2-nand";

			reg = <0 0 4>;		/* CS0, offset 0, NAND I/O window 4 */

			interrupt-parent = <&gpmc>;

			interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;

			nand-bus-width = <16>;

			ti,nand-ecc-opt = "bch8";

			ti,nand-xfer-type = "polled";

			rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */



			gpmc,sync-clk-ps = <0>;

			gpmc,cs-on-ns = <0>;

arch/arm/mach-omap2/gpmc-nand.c

+1 −6
Original line number Diff line number Diff line
@@ -97,9 +97,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, 
	gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);



	memset(&s, 0, sizeof(struct gpmc_settings));

	if (gpmc_nand_data->of_node)

		gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);

	else

	gpmc_set_legacy(gpmc_nand_data, &s);



	s.device_nand = true;
@@ -121,8 +118,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, 
	if (err < 0)

		goto out_free_cs;



	gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);



	if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {

		pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");

		err = -EINVAL;

drivers/memory/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ config TI_EMIF 


config OMAP_GPMC

	bool

	select GPIOLIB

	help

	  This driver is for the General Purpose Memory Controller (GPMC)

	  present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows

drivers/memory/omap-gpmc.c

+417 −238

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