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Commit 42158660 authored by Zhao Yakui's avatar Zhao Yakui Committed by Eric Anholt
Browse files

drm/i915: Restore the DPLL calculation logic for 9xx platform 



The DPLL calculation logic for 9xx platform is changed in:
commit 652c393a
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Mon Aug 17 13:31:43 2009 -0700

    drm/i915: add dynamic clock frequency control

Maybe we will get the different M/N/P combination with that by using the
previous dpll calculation logic.

So restore the DPLL calculation logic for 9xx platform.

Signed-off-by: default avatarZhao Yakui <yakui.zhao@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent d1fcea6a

drivers/gpu/drm/i915/intel_display.c

+11 −10
Original line number Diff line number Diff line
@@ -706,7 +706,6 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 


	memset (best_clock, 0, sizeof (*best_clock));



	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {

	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;

	     clock.m1++) {

		for (clock.m2 = limit->m2.min;
@@ -716,6 +715,8 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 
				break;

			for (clock.n = limit->n.min;

			     clock.n <= limit->n.max; clock.n++) {

				for (clock.p1 = limit->p1.min;

					clock.p1 <= limit->p1.max; clock.p1++) {

					int this_err;



					intel_clock(dev, refclk, &clock);