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Commit 41977e86 authored by Roman Yeryomin's avatar Roman Yeryomin Committed by Kalle Valo
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rt2x00: add support for MT7620



Basic support for MT7620 built-in wireless radio was added to
OpenWrt in r41441. It has seen some heavy cleaning and refactoring
since in order to match the Kernel's code quality standards.

Signed-off-by: default avatarRoman Yeryomin <roman@advem.lv>
Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Acked-by: default avatarStanislaw Gruszka <sgruszka@redhat.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent ca260ece
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+1 −1
Original line number Diff line number Diff line
@@ -201,7 +201,7 @@ endif

config RT2800SOC
	tristate "Ralink WiSoC support"
	depends on SOC_RT288X || SOC_RT305X
	depends on SOC_RT288X || SOC_RT305X || SOC_MT7620
	select RT2X00_LIB_SOC
	select RT2X00_LIB_MMIO
	select RT2X00_LIB_CRYPTO
+177 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@
#define RF5372				0x5372
#define RF5390				0x5390
#define RF5392				0x5392
#define RF7620				0x7620

/*
 * Chipset revisions.
@@ -638,6 +639,24 @@
#define RF_CSR_CFG_WRITE		FIELD32(0x00010000)
#define RF_CSR_CFG_BUSY			FIELD32(0x00020000)

/*
 * MT7620 RF registers (reversed order)
 */
#define RF_CSR_CFG_DATA_MT7620		FIELD32(0x0000ff00)
#define RF_CSR_CFG_REGNUM_MT7620	FIELD32(0x03ff0000)
#define RF_CSR_CFG_WRITE_MT7620		FIELD32(0x00000010)
#define RF_CSR_CFG_BUSY_MT7620		FIELD32(0x00000001)

/* undocumented registers for calibration of new MAC */
#define RF_CONTROL0			0x0518
#define RF_BYPASS0			0x051c
#define RF_CONTROL1			0x0520
#define RF_BYPASS1			0x0524
#define RF_CONTROL2			0x0528
#define RF_BYPASS2			0x052c
#define RF_CONTROL3			0x0530
#define RF_BYPASS3			0x0534

/*
 * EFUSE_CSR: RT30x0 EEPROM
 */
@@ -1021,6 +1040,16 @@
#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE	FIELD32(0x00007f00)
#define AUTOWAKEUP_CFG_AUTOWAKE		FIELD32(0x00008000)

/*
 * MIMO_PS_CFG: MIMO Power-save Configuration
 */
#define MIMO_PS_CFG			0x1210
#define MIMO_PS_CFG_MMPS_BB_EN		FIELD32(0x00000001)
#define MIMO_PS_CFG_MMPS_RX_ANT_NUM	FIELD32(0x00000006)
#define MIMO_PS_CFG_MMPS_RF_EN		FIELD32(0x00000008)
#define MIMO_PS_CFG_RX_STBY_POL		FIELD32(0x00000010)
#define MIMO_PS_CFG_RX_RX_STBY0		FIELD32(0x00000020)

/*
 * EDCA_AC0_CFG:
 */
@@ -1095,6 +1124,12 @@
#define TX_PWR_CFG_0_OFDM6_CH1		FIELD32(0x00f00000)
#define TX_PWR_CFG_0_OFDM12_CH0		FIELD32(0x0f000000)
#define TX_PWR_CFG_0_OFDM12_CH1		FIELD32(0xf0000000)
/* bits for new 2T devices */
#define TX_PWR_CFG_0B_1MBS_2MBS		FIELD32(0x000000ff)
#define TX_PWR_CFG_0B_5MBS_11MBS		FIELD32(0x0000ff00)
#define TX_PWR_CFG_0B_6MBS_9MBS		FIELD32(0x00ff0000)
#define TX_PWR_CFG_0B_12MBS_18MBS	FIELD32(0xff000000)


/*
 * TX_PWR_CFG_1:
@@ -1117,6 +1152,11 @@
#define TX_PWR_CFG_1_MCS0_CH1		FIELD32(0x00f00000)
#define TX_PWR_CFG_1_MCS2_CH0		FIELD32(0x0f000000)
#define TX_PWR_CFG_1_MCS2_CH1		FIELD32(0xf0000000)
/* bits for new 2T devices */
#define TX_PWR_CFG_1B_24MBS_36MBS	FIELD32(0x000000ff)
#define TX_PWR_CFG_1B_48MBS		FIELD32(0x0000ff00)
#define TX_PWR_CFG_1B_MCS0_MCS1		FIELD32(0x00ff0000)
#define TX_PWR_CFG_1B_MCS2_MCS3		FIELD32(0xff000000)

/*
 * TX_PWR_CFG_2:
@@ -1139,6 +1179,11 @@
#define TX_PWR_CFG_2_MCS8_CH1		FIELD32(0x00f00000)
#define TX_PWR_CFG_2_MCS10_CH0		FIELD32(0x0f000000)
#define TX_PWR_CFG_2_MCS10_CH1		FIELD32(0xf0000000)
/* bits for new 2T devices */
#define TX_PWR_CFG_2B_MCS4_MCS5		FIELD32(0x000000ff)
#define TX_PWR_CFG_2B_MCS6_MCS7		FIELD32(0x0000ff00)
#define TX_PWR_CFG_2B_MCS8_MCS9		FIELD32(0x00ff0000)
#define TX_PWR_CFG_2B_MCS10_MCS11	FIELD32(0xff000000)

/*
 * TX_PWR_CFG_3:
@@ -1161,6 +1206,11 @@
#define TX_PWR_CFG_3_STBC0_CH1		FIELD32(0x00f00000)
#define TX_PWR_CFG_3_STBC2_CH0		FIELD32(0x0f000000)
#define TX_PWR_CFG_3_STBC2_CH1		FIELD32(0xf0000000)
/* bits for new 2T devices */
#define TX_PWR_CFG_3B_MCS12_MCS13	FIELD32(0x000000ff)
#define TX_PWR_CFG_3B_MCS14		FIELD32(0x0000ff00)
#define TX_PWR_CFG_3B_STBC_MCS0_MCS1	FIELD32(0x00ff0000)
#define TX_PWR_CFG_3B_STBC_MCS2_MSC3	FIELD32(0xff000000)

/*
 * TX_PWR_CFG_4:
@@ -1175,6 +1225,9 @@
#define TX_PWR_CFG_4_STBC4_CH1		FIELD32(0x000000f0)
#define TX_PWR_CFG_4_STBC6_CH0		FIELD32(0x00000f00)
#define TX_PWR_CFG_4_STBC6_CH1		FIELD32(0x0000f000)
/* bits for new 2T devices */
#define TX_PWR_CFG_4B_STBC_MCS4_MCS5	FIELD32(0x000000ff)
#define TX_PWR_CFG_4B_STBC_MCS6		FIELD32(0x0000ff00)

/*
 * TX_PIN_CFG:
@@ -1201,6 +1254,8 @@
#define TX_PIN_CFG_RFTR_POL		FIELD32(0x00020000)
#define TX_PIN_CFG_TRSW_EN		FIELD32(0x00040000)
#define TX_PIN_CFG_TRSW_POL		FIELD32(0x00080000)
#define TX_PIN_CFG_RFRX_EN		FIELD32(0x00100000)
#define TX_PIN_CFG_RFRX_POL		FIELD32(0x00200000)
#define TX_PIN_CFG_PA_PE_A2_EN		FIELD32(0x01000000)
#define TX_PIN_CFG_PA_PE_G2_EN		FIELD32(0x02000000)
#define TX_PIN_CFG_PA_PE_A2_POL		FIELD32(0x04000000)
@@ -1547,6 +1602,95 @@
#define TX_PWR_CFG_4_EXT_STBC4_CH2	FIELD32(0x0000000f)
#define TX_PWR_CFG_4_EXT_STBC6_CH2	FIELD32(0x00000f00)

/* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2]
 * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB
 */
#define TX0_RF_GAIN_CORRECT		0x13a0
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_0	FIELD32(0x0000003f)
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_1	FIELD32(0x00003f00)
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_2	FIELD32(0x003f0000)
#define TX0_RF_GAIN_CORRECT_GAIN_CORR_3	FIELD32(0x3f000000)

#define TX1_RF_GAIN_CORRECT		0x13a4
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_0	FIELD32(0x0000003f)
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_1	FIELD32(0x00003f00)
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_2	FIELD32(0x003f0000)
#define TX1_RF_GAIN_CORRECT_GAIN_CORR_3	FIELD32(0x3f000000)

/* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level
 * Format: 7-bit, signed value
 * Unit: 0.5 dB, Range: -20 dB to -5 dB
 */
#define TX0_RF_GAIN_ATTEN		0x13a8
#define TX0_RF_GAIN_ATTEN_LEVEL_0	FIELD32(0x0000007f)
#define TX0_RF_GAIN_ATTEN_LEVEL_1	FIELD32(0x00007f00)
#define TX0_RF_GAIN_ATTEN_LEVEL_2	FIELD32(0x007f0000)
#define TX0_RF_GAIN_ATTEN_LEVEL_3	FIELD32(0x7f000000)
#define TX1_RF_GAIN_ATTEN		0x13ac
#define TX1_RF_GAIN_ATTEN_LEVEL_0	FIELD32(0x0000007f)
#define TX1_RF_GAIN_ATTEN_LEVEL_1	FIELD32(0x00007f00)
#define TX1_RF_GAIN_ATTEN_LEVEL_2	FIELD32(0x007f0000)
#define TX1_RF_GAIN_ATTEN_LEVEL_3	FIELD32(0x7f000000)

/* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0
 * TX_ALC_LIMIT_n: TXn upper limit
 * TX_ALC_CH_INIT_n: TXn channel initial transmission gain
 * Unit: 0.5 dB, Range: 0 to 23.5 dB
 */
#define TX_ALC_CFG_0			0x13b0
#define TX_ALC_CFG_0_CH_INIT_0		FIELD32(0x0000003f)
#define TX_ALC_CFG_0_CH_INIT_1		FIELD32(0x00003f00)
#define TX_ALC_CFG_0_LIMIT_0		FIELD32(0x003f0000)
#define TX_ALC_CFG_0_LIMIT_1		FIELD32(0x3f000000)

/* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1
 * TX_TEMP_COMP:      TX Power Temperature Compensation
 *                    Unit: 0.5 dB, Range: -10 dB to 10 dB
 * TXn_GAIN_FINE:     TXn Gain Fine Adjustment
 *                    Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB
 * RF_TOS_DLY:        Sets the RF_TOS_EN assertion delay after
 *                    deassertion of PA_PE.
 *                    Unit: 0.25 usec
 * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector
 * RF_TOS_TIMEOUT:    time-out value for RF_TOS_ENABLE
 *                    deassertion if RF_TOS_DONE is missing.
 *                    Unit: 0.25 usec
 * RF_TOS_ENABLE:     TX offset calibration enable
 * ROS_BUSY_EN:       RX offset calibration busy enable
 */
#define TX_ALC_CFG_1			0x13b4
#define TX_ALC_CFG_1_TX_TEMP_COMP	FIELD32(0x0000003f)
#define TX_ALC_CFG_1_TX0_GAIN_FINE	FIELD32(0x00000f00)
#define TX_ALC_CFG_1_TX1_GAIN_FINE	FIELD32(0x0000f000)
#define TX_ALC_CFG_1_RF_TOS_DLY		FIELD32(0x00070000)
#define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN	FIELD32(0x00300000)
#define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN	FIELD32(0x00c00000)
#define TX_ALC_CFG_1_RF_TOS_TIMEOUT	FIELD32(0x3f000000)
#define TX_ALC_CFG_1_RF_TOS_ENABLE	FIELD32(0x40000000)
#define TX_ALC_CFG_1_ROS_BUSY_EN	FIELD32(0x80000000)

/* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level
 * Format: 5-bit signed values
 * Unit: 0.5 dB, Range: -8 dB to 7 dB
 */
#define TX0_BB_GAIN_ATTEN		0x13c0
#define TX0_BB_GAIN_ATTEN_LEVEL_0	FIELD32(0x0000001f)
#define TX0_BB_GAIN_ATTEN_LEVEL_1	FIELD32(0x00001f00)
#define TX0_BB_GAIN_ATTEN_LEVEL_2	FIELD32(0x001f0000)
#define TX0_BB_GAIN_ATTEN_LEVEL_3	FIELD32(0x1f000000)
#define TX1_BB_GAIN_ATTEN		0x13c4
#define TX1_BB_GAIN_ATTEN_LEVEL_0	FIELD32(0x0000001f)
#define TX1_BB_GAIN_ATTEN_LEVEL_1	FIELD32(0x00001f00)
#define TX1_BB_GAIN_ATTEN_LEVEL_2	FIELD32(0x001f0000)
#define TX1_BB_GAIN_ATTEN_LEVEL_3	FIELD32(0x1f000000)

/* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */
#define TX_ALC_VGA3			0x13c8
#define TX_ALC_VGA3_TX0_ALC_VGA3	FIELD32(0x0000001f)
#define TX_ALC_VGA3_TX1_ALC_VGA3	FIELD32(0x00001f00)
#define TX_ALC_VGA3_TX0_ALC_VGA2	FIELD32(0x001f0000)
#define TX_ALC_VGA3_TX1_ALC_VGA2	FIELD32(0x1f000000)

/* TX_PWR_CFG_7 */
#define TX_PWR_CFG_7			0x13d4
#define TX_PWR_CFG_7_OFDM54_CH0		FIELD32(0x0000000f)
@@ -1555,6 +1699,10 @@
#define TX_PWR_CFG_7_MCS7_CH0		FIELD32(0x000f0000)
#define TX_PWR_CFG_7_MCS7_CH1		FIELD32(0x00f00000)
#define TX_PWR_CFG_7_MCS7_CH2		FIELD32(0x0f000000)
/* bits for new 2T devices */
#define TX_PWR_CFG_7B_54MBS		FIELD32(0x000000ff)
#define TX_PWR_CFG_7B_MCS7		FIELD32(0x00ff0000)


/* TX_PWR_CFG_8 */
#define TX_PWR_CFG_8			0x13d8
@@ -1564,12 +1712,17 @@
#define TX_PWR_CFG_8_MCS23_CH0		FIELD32(0x000f0000)
#define TX_PWR_CFG_8_MCS23_CH1		FIELD32(0x00f00000)
#define TX_PWR_CFG_8_MCS23_CH2		FIELD32(0x0f000000)
/* bits for new 2T devices */
#define TX_PWR_CFG_8B_MCS15		FIELD32(0x000000ff)


/* TX_PWR_CFG_9 */
#define TX_PWR_CFG_9			0x13dc
#define TX_PWR_CFG_9_STBC7_CH0		FIELD32(0x0000000f)
#define TX_PWR_CFG_9_STBC7_CH1		FIELD32(0x000000f0)
#define TX_PWR_CFG_9_STBC7_CH2		FIELD32(0x00000f00)
/* bits for new 2T devices */
#define TX_PWR_CFG_9B_STBC_MCS7		FIELD32(0x000000ff)

/*
 * RX_FILTER_CFG: RX configuration register.
@@ -2137,11 +2290,14 @@ struct mac_iveiv_entry {
#define RFCSR1_TX1_PD			FIELD8(0x20)
#define RFCSR1_RX2_PD			FIELD8(0x40)
#define RFCSR1_TX2_PD			FIELD8(0x80)
#define RFCSR1_TX2_EN_MT7620		FIELD8(0x02)

/*
 * RFCSR 2:
 */
#define RFCSR2_RESCAL_EN		FIELD8(0x80)
#define RFCSR2_RX2_EN_MT7620		FIELD8(0x02)
#define RFCSR2_TX2_EN_MT7620		FIELD8(0x20)

/*
 * RFCSR 3:
@@ -2159,6 +2315,12 @@ struct mac_iveiv_entry {
#define RFCSR3_BIT4			FIELD8(0x10)
#define RFCSR3_BIT5			FIELD8(0x20)

/*
 * RFCSR 4:
 * VCOCAL_EN used by MT7620
 */
#define RFCSR4_VCOCAL_EN		FIELD8(0x80)

/*
 * FRCSR 5:
 */
@@ -2214,6 +2376,7 @@ struct mac_iveiv_entry {
 */
#define RFCSR13_TX_POWER		FIELD8(0x1f)
#define RFCSR13_DR0			FIELD8(0xe0)
#define RFCSR13_RDIV_MT7620		FIELD8(0x03)

/*
 * RFCSR 15:
@@ -2224,6 +2387,8 @@ struct mac_iveiv_entry {
 * RFCSR 16:
 */
#define RFCSR16_TXMIXER_GAIN		FIELD8(0x07)
#define RFCSR16_RF_PLL_FREQ_SEL_MT7620	FIELD8(0x0F)
#define RFCSR16_SDM_MODE_MT7620		FIELD8(0xE0)

/*
 * RFCSR 17:
@@ -2236,6 +2401,8 @@ struct mac_iveiv_entry {
/* RFCSR 18 */
#define RFCSR18_XO_TUNE_BYPASS		FIELD8(0x40)

/* RFCSR 19 */
#define RFCSR19_K			FIELD8(0x03)

/*
 * RFCSR 20:
@@ -2246,11 +2413,14 @@ struct mac_iveiv_entry {
 * RFCSR 21:
 */
#define RFCSR21_RX_LO2_EN		FIELD8(0x08)
#define RFCSR21_BIT1			FIELD8(0x01)
#define RFCSR21_BIT8			FIELD8(0x80)

/*
 * RFCSR 22:
 */
#define RFCSR22_BASEBAND_LOOPBACK	FIELD8(0x01)
#define RFCSR22_FREQPLAN_D_MT7620	FIELD8(0x07)

/*
 * RFCSR 23:
@@ -2272,6 +2442,11 @@ struct mac_iveiv_entry {
#define RFCSR27_R3			FIELD8(0x30)
#define RFCSR27_R4			FIELD8(0x40)

/*
 * RFCSR 28:
 */
#define RFCSR28_CH11_HT40		FIELD8(0x04)

/*
 * RFCSR 29:
 */
@@ -2333,6 +2508,7 @@ struct mac_iveiv_entry {
 */
#define RFCSR42_BIT1			FIELD8(0x01)
#define RFCSR42_BIT4			FIELD8(0x08)
#define RFCSR42_TX2_EN_MT7620		FIELD8(0x40)

/*
 * RFCSR 49:
@@ -2435,6 +2611,7 @@ enum rt2800_eeprom_word {
	EEPROM_TSSI_BOUND_BG5,
	EEPROM_TXPOWER_A1,
	EEPROM_TXPOWER_A2,
	EEPROM_TXPOWER_INIT,
	EEPROM_TSSI_BOUND_A1,
	EEPROM_TSSI_BOUND_A2,
	EEPROM_TSSI_BOUND_A3,
+1395 −26

File changed.

Preview size limit exceeded, changes collapsed.

+4 −0
Original line number Diff line number Diff line
@@ -33,6 +33,10 @@
struct rt2800_drv_data {
	u8 calibration_bw20;
	u8 calibration_bw40;
	char rx_calibration_bw20;
	char rx_calibration_bw40;
	char tx_calibration_bw20;
	char tx_calibration_bw40;
	u8 bbp25;
	u8 bbp26;
	u8 txmixer_gain_24g;
+1 −0
Original line number Diff line number Diff line
@@ -174,6 +174,7 @@ struct rt2x00_chip {
#define RT5390		0x5390  /* 2.4GHz */
#define RT5392		0x5392  /* 2.4GHz */
#define RT5592		0x5592
#define RT6352		0x6352  /* WSOC 2.4GHz */

	u16 rf;
	u16 rev;