Commit 415544d5 authored Oct 10, 2017 by Sagar Arun Kamble Committed by Chris Wilson Oct 11, 2017

drm/i915: Remove superfluous IS_BDW checks and non-BDW changes from gen8_enable_rps



This patch removes all IS_BROADWELL checks and non-BDW changes from
gen8_enable_rps as it is called only for BROADWELL.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-3-git-send-email-sagar.a.kamble@intel.com


Acked-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-2-chris@chris-wilson.co.uk

parent 960e5465

drivers/gpu/drm/i915/intel_pm.c

+5 −12

Original line number	Diff line number	Diff line
		@@ -6644,23 +6644,16 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
		for_each_engine(engine, dev_priv, id)
		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
		I915_WRITE(GEN6_RC_SLEEP, 0);
		if (IS_BROADWELL(dev_priv))
		I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
		else
		I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */

		/* 3: Enable RC6 */
		if (intel_enable_rc6() & INTEL_RC6_ENABLE)
		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
		intel_print_rc6_info(dev_priv, rc6_mask);
		if (IS_BROADWELL(dev_priv))

		I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE \|
		GEN7_RC_CTL_TO_MODE \|
		rc6_mask);
		else
		I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE \|
		GEN6_RC_CTL_EI_MODE(1) \|
		rc6_mask);

		/* 4 Program defaults and thresholds for RPS*/
		I915_WRITE(GEN6_RPNSWREQ,