Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4139829c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-nouveau-next' of... 

Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

This is bigger because it regenerates the internal firmwares after a fix.

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nouveau/doc: update the thermal documentation
  drm/nouveau/pwr: fix typo in fifo wrap handling
  drm/nv50/disp: fix a potential oops in supervisor handling
  drm/nouveau/disp/dp: don't touch link config after success
  drm/nouveau/kms: reference vblank for crtc during pageflip.
  drm/gk104/fb/ram: fixups from an earlier search+replace
  drm/nv50/gr: remove an unneeded write while initialising PGRAPH
  drm/nv50/gr: fix overlap while zeroing zcull regions
  drm/gf100-/gr: report class data to host on fwmthd failure
  drm/gk104/ibus: increase various random timeouts
  drm/gk104/clk: only touch divider for mode we'll be using
parents 7171511e 0946807a

Documentation/thermal/nouveau_thermal

+4 −3
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ Kernel driver nouveau 
Supported chips:

* NV43+



Authors: Martin Peres (mupuf) <martin.peres@labri.fr>

Authors: Martin Peres (mupuf) <martin.peres@free.fr>



Description

---------
@@ -68,8 +68,9 @@ Your fan can be driven in different modes: 


NOTE: Be sure to use the manual mode if you want to drive the fan speed manually



NOTE2: Not all fan management modes may be supported on all chipsets. We are

working on it.

NOTE2: When operating in manual mode outside the vbios-defined

[PWM_min, PWM_max] range, the reported fan speed (RPM) may not be accurate

depending on your hardware.



Bug reports

---------

drivers/gpu/drm/nouveau/core/engine/disp/dport.c

+3 −4
Original line number Diff line number Diff line
@@ -241,7 +241,9 @@ dp_link_train_eq(struct dp_state *dp) 
		dp_set_training_pattern(dp, 2);



	do {

		if (dp_link_train_update(dp, dp->pc2, 400))

		if ((tries &&

		    dp_link_train_commit(dp, dp->pc2)) ||

		    dp_link_train_update(dp, dp->pc2, 400))

			break;



		eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
@@ -253,9 +255,6 @@ dp_link_train_eq(struct dp_state *dp) 
			    !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))

				eq_done = false;

		}



		if (dp_link_train_commit(dp, dp->pc2))

			break;

	} while (!eq_done && cr_done && ++tries <= 5);



	return eq_done ? 0 : -1;

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+1 −1
Original line number Diff line number Diff line
@@ -1270,7 +1270,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) 
	i--;



	outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);

	if (!data)

	if (!outp)

		return NULL;



	if (outp->info.location == 0) {

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ mmio_list_base: 
#ifdef INCLUDE_CODE

// reports an exception to the host

//

// In: $r15 error code (see nvc0.fuc)

// In: $r15 error code (see os.h)

//

error:

	push $r14

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc

+15 −3
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ hub_mmio_list_next: 
#ifdef INCLUDE_CODE

// reports an exception to the host

//

// In: $r15 error code (see nvc0.fuc)

// In: $r15 error code (see os.h)

//

error:

	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
@@ -343,13 +343,25 @@ ih: 
	ih_no_ctxsw:

	and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD

	bra e #ih_no_fwmthd

		// none we handle, ack, and fall-through to unhandled

		// none we handle; report to host and ack

		nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO)

		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15)

		nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR)

		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15)

		extr $r14 $r15 16:18

		shl b32 $r14 $r14 2

		imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0))

		add b32 $r14 $r15

		call(nv_rd32)

		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15)

		mov $r15 E_BAD_FWMTHD

		call(error)

		mov $r11 0x100

		nv_wr32(0x400144, $r11)



	// anything we didn't handle, bring it to the host's attention

	ih_no_fwmthd:

	mov $r11 0x104 // FIFO | CHSW

	mov $r11 0x504 // FIFO | CHSW | FWMTHD

	not b32 $r11

	and $r11 $r10 $r11

	bra e #ih_no_other