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Commit 41241c17 authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
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Blackfin arch: Add missing definitions for BF561

parent 36208059
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+3 −0
Original line number Diff line number Diff line
@@ -55,6 +55,9 @@
/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define SWRST                   SICA_SWRST
#define SYSCR                   SICA_SYSCR
#define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
#define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
#define RESET_SOFTWARE          (SWRST_OCCURRED)

/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST              0xFFC00100	/* Software Reset register */