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Commit 400443e8 authored by Mikita Lipski's avatar Mikita Lipski Committed by Alex Deucher
Browse files

drm/amd/display: add a check for display depth validity 

[why]
HDMI 2.0 fails to validate 4K@60 timing with 10 bpc
[how]
Adding a helper function that would verify if the display depth
assigned would pass a bandwidth validation.
Drop the display depth by one level till calculated pixel clk
is lower than maximum TMDS clk.

Bugzilla: https://bugs.freedesktop.org/106959



Signed-off-by: default avatarMikita Lipski <mikita.lipski@amd.com>
Tested-by: default avatarMike Lothian <mike@fireburn.co.uk>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fe61a2f1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+42 −0
Original line number Diff line number Diff line
@@ -2176,6 +2176,46 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 
	return color_space;

}



static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)

{

	if (timing_out->display_color_depth <= COLOR_DEPTH_888)

		return;



	timing_out->display_color_depth--;

}



static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,

						const struct drm_display_info *info)

{

	int normalized_clk;

	if (timing_out->display_color_depth <= COLOR_DEPTH_888)

		return;

	do {

		normalized_clk = timing_out->pix_clk_khz;

		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */

		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)

			normalized_clk /= 2;

		/* Adjusting pix clock following on HDMI spec based on colour depth */

		switch (timing_out->display_color_depth) {

		case COLOR_DEPTH_101010:

			normalized_clk = (normalized_clk * 30) / 24;

			break;

		case COLOR_DEPTH_121212:

			normalized_clk = (normalized_clk * 36) / 24;

			break;

		case COLOR_DEPTH_161616:

			normalized_clk = (normalized_clk * 48) / 24;

			break;

		default:

			return;

		}

		if (normalized_clk <= info->max_tmds_clock)

			return;

		reduce_mode_colour_depth(timing_out);



	} while (timing_out->display_color_depth > COLOR_DEPTH_888);



}

/*****************************************************************************/



static void
@@ -2232,6 +2272,8 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, 


	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;

	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;

	if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)

		adjust_colour_depth_from_display_info(timing_out, info);

}



static void fill_audio_info(struct audio_info *audio_info,