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Commit 3ff77275 authored by Zhangfei Gao's avatar Zhangfei Gao Committed by Stephen Boyd
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clk: hi6220: add acpu clock



Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by: default avatarZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: default avatarLi Pengcheng <lipengcheng8@huawei.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 6454504c
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+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required Properties:
- compatible: the compatible should be one of the following strings to
	indicate the clock controller functionality.

	- "hisilicon,hi6220-acpu-sctrl"
	- "hisilicon,hi6220-aoctrl"
	- "hisilicon,hi6220-sysctrl"
	- "hisilicon,hi6220-mediactrl"
+22 −0
Original line number Diff line number Diff line
@@ -285,3 +285,25 @@ static void __init hi6220_clk_power_init(struct device_node *np)
				ARRAY_SIZE(hi6220_div_clks_power), clk_data);
}
CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);

/* clocks in acpu */
static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = {
	{ HI6220_ACPU_SFT_AT_S, "sft_at_s", "cs_atb",
	  CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, },
};

static void __init hi6220_clk_acpu_init(struct device_node *np)
{
	struct hisi_clock_data *clk_data;
	int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks);

	clk_data = hisi_clk_init(np, nr);
	if (!clk_data)
		return;

	hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks,
				   ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks),
				   clk_data);
}

CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init);
+4 −0
Original line number Diff line number Diff line
@@ -174,4 +174,8 @@
#define HI6220_DDRC_AXI1	7

#define HI6220_POWER_NR_CLKS	8

/* clk in Hi6220 acpu sctrl */
#define HI6220_ACPU_SFT_AT_S		0

#endif