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Commit 3fbef2f9 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'arm-soc/for-4.15/drivers' of http://github.com/Broadcom/stblinux into next/drivers 

Pull "Broadcom drivers changes for 4.15" from Florian Fainelli:

This pull requests contains Broadcom SoCs drivers updates for 4.15, please pull
the following:

- Markus adds support for the Broadcom STB DDR PHY frontend which supports
  dynamic firmware loading and offers the ability to respond with DRAM refresh
  rates. He also adds a proper documentation binding document for that
  peripheral

- Brian adds support for S2/S3/S5 system suspend/resume modes on ARM-based SoCs
  which is not new but had been lingering for a long time.

- Justin adds S2/S3 system suspend/resume modes on MIPS-based SoCs which is a
  bit new newer and builds on top of the ARM-based support.

- Florian adds Device Tree binding documents for both ARM and MIPS based systems
  describing the necessary nodes for S2/S3/S5 on these SoCs.

(This pull request somehow missed the 4.14 merge window and is now being sent again
for 4.15 along with build fixes from Arnd).

* tag 'arm-soc/for-4.15/drivers' of http://github.com/Broadcom/stblinux:
  soc bcm: brcmstb: Add support for S2/S3/S5 suspend states (MIPS)
  dt-bindings: Document MIPS Broadcom STB power management nodes
  soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)
  dt-bindings: ARM: brcmstb: Update Broadcom STB Power Management binding
  memory: brcmstb: Add driver for DPFE
  dt-bindings: Add bindings for Broadcom STB DRAM Sensors
parents 8a5776a5 0e9b1141

Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt

+5 −1
Original line number Original line Diff line number Diff line
@@ -164,6 +164,8 @@ Control registers for this memory controller's DDR PHY. 




Required properties:

Required properties:

- compatible     : should contain one of these

- compatible     : should contain one of these

	"brcm,brcmstb-ddr-phy-v71.1"

	"brcm,brcmstb-ddr-phy-v72.0"

	"brcm,brcmstb-ddr-phy-v225.1"

	"brcm,brcmstb-ddr-phy-v225.1"

	"brcm,brcmstb-ddr-phy-v240.1"

	"brcm,brcmstb-ddr-phy-v240.1"

	"brcm,brcmstb-ddr-phy-v240.2"

	"brcm,brcmstb-ddr-phy-v240.2"
@@ -184,7 +186,9 @@ Sequencer DRAM parameters and control registers. Used for Self-Refresh 
Power-Down (SRPD), among other things.

Power-Down (SRPD), among other things.





Required properties:

Required properties:

- compatible     : should contain "brcm,brcmstb-memc-ddr"

- compatible     : should contain one of these

	"brcm,brcmstb-memc-ddr-rev-b.2.2"

	"brcm,brcmstb-memc-ddr"

- reg            : the MEMC DDR register range

- reg            : the MEMC DDR register range





Example:

Example:

Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt

0 → 100644
+27 −0
Original line number Original line Diff line number Diff line 
DDR PHY Front End (DPFE) for Broadcom STB

=========================================



DPFE and the DPFE firmware provide an interface for the host CPU to

communicate with the DCPU, which resides inside the DDR PHY.



There are three memory regions for interacting with the DCPU. These are

specified in a single reg property.



Required properties:

  - compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu"

    or "brcm,dpfe-cpu"

  - reg: must reference three register ranges

      - start address and length of the DCPU register space

      - start address and length of the DCPU data memory space

      - start address and length of the DCPU instruction memory space

  - reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem";

        they must be in the same order as the register declarations



Example:

	dpfe_cpu0: dpfe-cpu@f1132000 {

		compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";

		reg =  <0xf1132000 0x180

			0xf1134000 0x1000

			0xf1138000 0x4000>;

		reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";

	};

Documentation/devicetree/bindings/mips/brcm/soc.txt

+153 −0
Original line number Original line Diff line number Diff line
@@ -11,3 +11,156 @@ Required properties: 




The experimental -viper variants are for running Linux on the 3384's

The experimental -viper variants are for running Linux on the 3384's

BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.

BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.



Power management

----------------



For power management (particularly, S2/S3/S5 system suspend), the following SoC

components are needed:



= Always-On control block (AON CTRL)



This hardware provides control registers for the "always-on" (even in low-power

modes) hardware, such as the Power Management State Machine (PMSM).



Required properties:

- compatible     : should be one of

		   "brcm,bcm7425-aon-ctrl"

		   "brcm,bcm7429-aon-ctrl"

		   "brcm,bcm7435-aon-ctrl" and

		   "brcm,brcmstb-aon-ctrl"

- reg            : the register start and length for the AON CTRL block



Example:



syscon@410000 {

	compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";

	reg = <0x410000 0x400>;

};



= Memory controllers



A Broadcom STB SoC typically has a number of independent memory controllers,

each of which may have several associated hardware blocks, which are versioned

independently (control registers, DDR PHYs, etc.). One might consider

describing these controllers as a parent "memory controllers" block, which

contains N sub-nodes (one for each controller in the system), each of which is

associated with a number of hardware register resources (e.g., its PHY.



== MEMC (MEMory Controller)



Represents a single memory controller instance.



Required properties:

- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"

- ranges	 : should contain the child address in the parent address

		   space, must be 0 here, and the register start and length of

		   the entire memory controller (including all sub nodes: DDR PHY,

		   arbiter, etc.)

- #address-cells : must be 1

- #size-cells	 : must be 1



Example:



	memory-controller@0 {

		compatible = "brcm,brcmstb-memc", "simple-bus";

		ranges = <0x0 0x0 0xa000>;

		#address-cells = <1>;

		#size-cells = <1>;



		memc-arb@1000 {

			...

		};



		memc-ddr@2000 {

			...

		};



		ddr-phy@6000 {

			...

		};

	};



Should contain subnodes for any of the following relevant hardware resources:



== DDR PHY control



Control registers for this memory controller's DDR PHY.



Required properties:

- compatible     : should contain one of these

		   "brcm,brcmstb-ddr-phy-v64.5"

		   "brcm,brcmstb-ddr-phy"



- reg            : the DDR PHY register range and length



Example:



	ddr-phy@6000 {

		compatible = "brcm,brcmstb-ddr-phy-v64.5";

		reg = <0x6000 0xc8>;

	};



== DDR memory controller sequencer



Control registers for this memory controller's DDR memory sequencer



Required properties:

- compatible     : should contain one of these

		   "brcm,bcm7425-memc-ddr"

		   "brcm,bcm7429-memc-ddr"

		   "brcm,bcm7435-memc-ddr" and

		   "brcm,brcmstb-memc-ddr"



- reg            : the DDR sequencer register range and length



Example:



	memc-ddr@2000 {

		compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";

		reg = <0x2000 0x300>;

	};



== MEMC Arbiter



The memory controller arbiter is responsible for memory clients allocation

(bandwidth, priorities etc.) and needs to have its contents restored during

deep sleep states (S3).



Required properties:



- compatible	: should contain one of these

		  "brcm,brcmstb-memc-arb-v10.0.0.0"

		  "brcm,brcmstb-memc-arb"



- reg		: the DDR Arbiter register range and length



Example:



	memc-arb@1000 {

		compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";

		reg = <0x1000 0x248>;

	};



== Timers



The Broadcom STB chips contain a timer block with several general purpose

timers that can be used.



Required properties:



- compatible	: should contain one of:

		  "brcm,bcm7425-timers"

		  "brcm,bcm7429-timers"

		  "brcm,bcm7435-timers and

		  "brcm,brcmstb-timers"

- reg		: the timers register range

- interrupts	: the interrupt line for this timer block



Example:



	timers: timer@4067c0 {

		compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";

		reg = <0x4067c0 0x40>;

		interrupts = <&periph_intc 19>;

	};

MAINTAINERS

+8 −0
Original line number Original line Diff line number Diff line
@@ -2974,6 +2974,14 @@ L: bcm-kernel-feedback-list@broadcom.com 
S:	Maintained

S:	Maintained

F:	drivers/mtd/nand/brcmnand/

F:	drivers/mtd/nand/brcmnand/





BROADCOM STB DPFE DRIVER

M:	Markus Mayer <mmayer@broadcom.com>

M:	bcm-kernel-feedback-list@broadcom.com

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt

F:	drivers/memory/brcmstb_dpfe.c



BROADCOM SYSTEMPORT ETHERNET DRIVER

BROADCOM SYSTEMPORT ETHERNET DRIVER

M:	Florian Fainelli <f.fainelli@gmail.com>

M:	Florian Fainelli <f.fainelli@gmail.com>

L:	netdev@vger.kernel.org

L:	netdev@vger.kernel.org

drivers/memory/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -8,6 +8,7 @@ endif 
obj-$(CONFIG_ARM_PL172_MPMC)	+= pl172.o

obj-$(CONFIG_ARM_PL172_MPMC)	+= pl172.o

obj-$(CONFIG_ATMEL_SDRAMC)	+= atmel-sdramc.o

obj-$(CONFIG_ATMEL_SDRAMC)	+= atmel-sdramc.o

obj-$(CONFIG_ATMEL_EBI)		+= atmel-ebi.o

obj-$(CONFIG_ATMEL_EBI)		+= atmel-ebi.o

obj-$(CONFIG_ARCH_BRCMSTB)	+= brcmstb_dpfe.o

obj-$(CONFIG_TI_AEMIF)		+= ti-aemif.o

obj-$(CONFIG_TI_AEMIF)		+= ti-aemif.o

obj-$(CONFIG_TI_EMIF)		+= emif.o

obj-$(CONFIG_TI_EMIF)		+= emif.o

obj-$(CONFIG_OMAP_GPMC)		+= omap-gpmc.o

obj-$(CONFIG_OMAP_GPMC)		+= omap-gpmc.o