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Commit 3f7f3b0f authored by Shunqian Zheng's avatar Shunqian Zheng Committed by Heiko Stuebner
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arm64: dts: rockchip: assign clock rate for ACLK_VIO on rk3399 



The ACLK_VIO is a parent clock used by a several children,
its suggested clock rate is 400MHz. Right now it gets 400MHz
because it sources from CPLL(800M) and divides by 2 after reset.
It's good not to rely on default values like this, so let's
explicitly set it.
NOTE: it's expected that at least one board may override cru node and
set the CPLL to 1.6 GHz. On that board it will be very important to be
explicit about aclk-vio being 400 MHz.

Signed-off-by: default avatarShunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 0626d183

arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -586,7 +586,8 @@ 
		<&cru PCLK_PERIHP>,

		<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,

		<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,

		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;

		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,

		<&cru ACLK_VIO>;

	assigned-clock-rates =

		<600000000>, <800000000>,

		<1000000000>,
@@ -594,7 +595,8 @@ 
		<37500000>,

		<100000000>, <100000000>,

		<50000000>, <800000000>,

		<100000000>, <50000000>;

		<100000000>, <50000000>,

		<400000000>;

};



&emmc_phy {

arch/arm64/boot/dts/rockchip/rk3399.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -1322,7 +1322,8 @@ 
			<&cru PCLK_PERIHP>,

			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,

			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,

			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;

			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,

			<&cru ACLK_VIO>;

		assigned-clock-rates =

			 <594000000>,  <800000000>,

			<1000000000>,
@@ -1330,7 +1331,8 @@ 
			  <37500000>,

			 <100000000>,  <100000000>,

			  <50000000>, <600000000>,

			 <100000000>,   <50000000>;

			 <100000000>,   <50000000>,

			 <400000000>;

	};



	grf: syscon@ff770000 {