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Commit 3f2f4dc4 authored by Yinghai Lu's avatar Yinghai Lu Committed by Bjorn Helgaas
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PCI: Pass bridge device, not bus, when updating bridge windows 

pci_setup_bridge_io(), pci_setup_bridge_mmio(), and
pci_setup_bridge_mmio_pref() program the windows of PCI-PCI bridges.
Previously they accepted a pointer to the pci_bus of the secondary bus,
then looked up the bridge leading to that bus.  Pass the bridge directly,
which will make it more convenient for future callers.

No functional change.

[bhelgaas: changelog, split into separate patch]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=85491


Reported-by: default avatarMarek Kordik <kordikmarek@gmail.com>
Fixes: 5b285415 ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.16+
parent c3e59ee4

drivers/pci/setup-bus.c

+9 −12
Original line number Diff line number Diff line
@@ -530,9 +530,8 @@ EXPORT_SYMBOL(pci_setup_cardbus); 
   config space writes, so it's quite possible that an I/O window of

   the bridge will have some undesirable address (e.g. 0) after the

   first write. Ditto 64-bit prefetchable MMIO.  */

static void pci_setup_bridge_io(struct pci_bus *bus)

static void pci_setup_bridge_io(struct pci_dev *bridge)

{

	struct pci_dev *bridge = bus->self;

	struct resource *res;

	struct pci_bus_region region;

	unsigned long io_mask;
@@ -545,7 +544,7 @@ static void pci_setup_bridge_io(struct pci_bus *bus) 
		io_mask = PCI_IO_1K_RANGE_MASK;



	/* Set up the top and bottom of the PCI I/O segment for this bus. */

	res = bus->resource[0];

	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];

	pcibios_resource_to_bus(bridge->bus, &region, res);

	if (res->flags & IORESOURCE_IO) {

		pci_read_config_word(bridge, PCI_IO_BASE, &l);
@@ -568,15 +567,14 @@ static void pci_setup_bridge_io(struct pci_bus *bus) 
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);

}



static void pci_setup_bridge_mmio(struct pci_bus *bus)

static void pci_setup_bridge_mmio(struct pci_dev *bridge)

{

	struct pci_dev *bridge = bus->self;

	struct resource *res;

	struct pci_bus_region region;

	u32 l;



	/* Set up the top and bottom of the PCI Memory segment for this bus. */

	res = bus->resource[1];

	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];

	pcibios_resource_to_bus(bridge->bus, &region, res);

	if (res->flags & IORESOURCE_MEM) {

		l = (region.start >> 16) & 0xfff0;
@@ -588,9 +586,8 @@ static void pci_setup_bridge_mmio(struct pci_bus *bus) 
	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);

}



static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)

static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)

{

	struct pci_dev *bridge = bus->self;

	struct resource *res;

	struct pci_bus_region region;

	u32 l, bu, lu;
@@ -602,7 +599,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) 


	/* Set up PREF base/limit. */

	bu = lu = 0;

	res = bus->resource[2];

	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];

	pcibios_resource_to_bus(bridge->bus, &region, res);

	if (res->flags & IORESOURCE_PREFETCH) {

		l = (region.start >> 16) & 0xfff0;
@@ -630,13 +627,13 @@ static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) 
		 &bus->busn_res);



	if (type & IORESOURCE_IO)

		pci_setup_bridge_io(bus);

		pci_setup_bridge_io(bridge);



	if (type & IORESOURCE_MEM)

		pci_setup_bridge_mmio(bus);

		pci_setup_bridge_mmio(bridge);



	if (type & IORESOURCE_PREFETCH)

		pci_setup_bridge_mmio_pref(bus);

		pci_setup_bridge_mmio_pref(bridge);



	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);

}