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Commit 3f1f0b1c authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-2017-12-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 

[airlied: fix conflict in intel_dsi.c]

drm-intel-next-2017-12-01:

- Init clock gate fix (Ville)
- Execlists event handling corrections (Chris, Michel)
- Improvements on GPU Cache invalidation and context switch (Chris)
- More perf OA changes (Lionel)
- More selftests improvements and fixes (Chris, Matthew)
- Clean-up on modules parameters (Chris)
- Clean-up around old ringbuffer submission and hw semaphore on old platforms (Chris)
- More Cannonlake stabilization effort (David, James)
- Display planes clean-up and improvements (Ville)
- New PMU interface for perf queries... (Tvrtko)
- ... and other subsequent PMU changes and fixes (Tvrtko, Chris)
- Remove success dmesg noise from rotation (Chris)
- New DMC for Kabylake (Anusha)
- Fixes around atomic commits (Daniel)
- GuC updates and fixes (Sagar, Michal, Chris)
- Couple gmbus/i2c fixes (Ville)
- Use exponential backoff for all our wait_for() (Chris)
- Fixes for i915/fbdev (Chris)
- Backlight fixes (Arnd)
- Updates on shrinker (Chris)
- Make Hotplug enable more robuts (Chris)
- Disable huge pages (TPH) on lack of a needed workaround (Joonas)
- New GuC images for SKL, KBL, BXT (Sagar)
- Add HW Workaround for Geminilake performance (Valtteri)
- Fixes for PPS timings (Imre)
- More IPS fixes (Maarten)
- Many fixes for Display Port on gen2-gen4 (Ville)
- Retry GPU reset making the recover from hang more robust (Chris)

* tag 'drm-intel-next-2017-12-01' of git://anongit.freedesktop.org/drm/drm-intel: (101 commits)
  drm/i915: Update DRIVER_DATE to 20171201
  drm/i915/cnl: Mask previous DDI - PLL mapping
  drm/i915: Remove unsafe i915.enable_rc6
  drm/i915: Sleep and retry a GPU reset if at first we don't succeed
  drm/i915: Interlaced DP output doesn't work on VLV/CHV
  drm/i915: Pass crtc state to intel_pipe_{enable,disable}()
  drm/i915: Wait for pipe to start on i830 as well
  drm/i915: Fix vblank timestamp/frame counter jumps on gen2
  drm/i915: Fix deadlock in i830_disable_pipe()
  drm/i915: Fix has_audio readout for DDI A
  drm/i915: Don't add the "force audio" property to DP connectors that don't support audio
  drm/i915: Disable DP audio for g4x
  drm/i915/selftests: Wake the device before executing requests on the GPU
  drm/i915: Set fake_vma.size as well as fake_vma.node.size for capture
  drm/i915: Tidy up signed/unsigned comparison
  drm/i915: Enable IPS with only sprite plane visible too, v4.
  drm/i915: Make ips_enabled a property depending on whether IPS is enabled, v3.
  drm/i915: Avoid PPS HW/SW state mismatch due to rounding
  drm/i915: Skip switch-to-kernel-context on suspend when wedged
  drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
  ...
parents 5c379b4f d65efe7c

drivers/gpu/drm/i915/Kconfig.debug

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ config DRM_I915_WERROR 
config DRM_I915_DEBUG

        bool "Enable additional driver debugging"

        depends on DRM_I915

        select DEBUG_FS

        select PREEMPT_COUNT

        select I2C_CHARDEV

        select DRM_DP_AUX_CHARDEV

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ i915-y := i915_drv.o \ 


i915-$(CONFIG_COMPAT)   += i915_ioc32.o

i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o

i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o



# GEM code

i915-y += i915_cmd_parser.o \

drivers/gpu/drm/i915/gvt/render.c

+1 −2
Original line number Diff line number Diff line
@@ -294,8 +294,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) 
		 * write.

		 */

		if (mmio->in_context &&

				((ctx_ctrl & inhibit_mask) != inhibit_mask) &&

				i915_modparams.enable_execlists)

		    (ctx_ctrl & inhibit_mask) != inhibit_mask)

			continue;



		if (mmio->mask)

drivers/gpu/drm/i915/i915_cmd_parser.c

+4 −3
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
 */



#include "i915_drv.h"

#include "intel_ringbuffer.h"



/**

 * DOC: batch buffer command parser
@@ -940,7 +941,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 
		return;

	}



	engine->needs_cmd_parser = true;

	engine->flags |= I915_ENGINE_NEEDS_CMD_PARSER;

}



/**
@@ -952,7 +953,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 
 */

void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)

{

	if (!engine->needs_cmd_parser)

	if (!intel_engine_needs_cmd_parser(engine))

		return;



	fini_hash_table(engine);
@@ -1350,7 +1351,7 @@ int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) 


	/* If the command parser is not enabled, report 0 - unsupported */

	for_each_engine(engine, dev_priv, id) {

		if (engine->needs_cmd_parser) {

		if (intel_engine_needs_cmd_parser(engine)) {

			active = true;

			break;

		}

drivers/gpu/drm/i915/i915_debugfs.c

+2 −141
Original line number Diff line number Diff line
@@ -1151,13 +1151,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;

		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;

		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;

		if (INTEL_GEN(dev_priv) >= 9)

			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;

		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;

		else

			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;

		cagf = intel_gpu_freq(dev_priv, cagf);

		cagf = intel_gpu_freq(dev_priv,

				      intel_get_cagf(dev_priv, rpstat));



		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
@@ -1989,75 +1984,6 @@ static int i915_context_status(struct seq_file *m, void *unused) 
	return 0;

}



static void i915_dump_lrc_obj(struct seq_file *m,

			      struct i915_gem_context *ctx,

			      struct intel_engine_cs *engine)

{

	struct i915_vma *vma = ctx->engine[engine->id].state;

	struct page *page;

	int j;



	seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);



	if (!vma) {

		seq_puts(m, "\tFake context\n");

		return;

	}



	if (vma->flags & I915_VMA_GLOBAL_BIND)

		seq_printf(m, "\tBound in GGTT at 0x%08x\n",

			   i915_ggtt_offset(vma));



	if (i915_gem_object_pin_pages(vma->obj)) {

		seq_puts(m, "\tFailed to get pages for context object\n\n");

		return;

	}



	page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);

	if (page) {

		u32 *reg_state = kmap_atomic(page);



		for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {

			seq_printf(m,

				   "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",

				   j * 4,

				   reg_state[j], reg_state[j + 1],

				   reg_state[j + 2], reg_state[j + 3]);

		}

		kunmap_atomic(reg_state);

	}



	i915_gem_object_unpin_pages(vma->obj);

	seq_putc(m, '\n');

}



static int i915_dump_lrc(struct seq_file *m, void *unused)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct drm_device *dev = &dev_priv->drm;

	struct intel_engine_cs *engine;

	struct i915_gem_context *ctx;

	enum intel_engine_id id;

	int ret;



	if (!i915_modparams.enable_execlists) {

		seq_printf(m, "Logical Ring Contexts are disabled\n");

		return 0;

	}



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;



	list_for_each_entry(ctx, &dev_priv->contexts.list, link)

		for_each_engine(engine, dev_priv, id)

			i915_dump_lrc_obj(m, ctx, engine);



	mutex_unlock(&dev->struct_mutex);



	return 0;

}



static const char *swizzle_string(unsigned swizzle)

{

	switch (swizzle) {
@@ -3304,69 +3230,6 @@ static int i915_shrinker_info(struct seq_file *m, void *unused) 
	return 0;

}



static int i915_semaphore_status(struct seq_file *m, void *unused)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct drm_device *dev = &dev_priv->drm;

	struct intel_engine_cs *engine;

	int num_rings = INTEL_INFO(dev_priv)->num_rings;

	enum intel_engine_id id;

	int j, ret;



	if (!i915_modparams.semaphores) {

		seq_puts(m, "Semaphores are disabled\n");

		return 0;

	}



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	if (IS_BROADWELL(dev_priv)) {

		struct page *page;

		uint64_t *seqno;



		page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);



		seqno = (uint64_t *)kmap_atomic(page);

		for_each_engine(engine, dev_priv, id) {

			uint64_t offset;



			seq_printf(m, "%s\n", engine->name);



			seq_puts(m, "  Last signal:");

			for (j = 0; j < num_rings; j++) {

				offset = id * I915_NUM_ENGINES + j;

				seq_printf(m, "0x%08llx (0x%02llx) ",

					   seqno[offset], offset * 8);

			}

			seq_putc(m, '\n');



			seq_puts(m, "  Last wait:  ");

			for (j = 0; j < num_rings; j++) {

				offset = id + (j * I915_NUM_ENGINES);

				seq_printf(m, "0x%08llx (0x%02llx) ",

					   seqno[offset], offset * 8);

			}

			seq_putc(m, '\n');



		}

		kunmap_atomic(seqno);

	} else {

		seq_puts(m, "  Last signal:");

		for_each_engine(engine, dev_priv, id)

			for (j = 0; j < num_rings; j++)

				seq_printf(m, "0x%08x\n",

					   I915_READ(engine->semaphore.mbox.signal[j]));

		seq_putc(m, '\n');

	}



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);

	return 0;

}



static int i915_shared_dplls_info(struct seq_file *m, void *unused)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4833,7 +4696,6 @@ static const struct drm_info_list i915_debugfs_list[] = { 
	{"i915_vbt", i915_vbt, 0},

	{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},

	{"i915_context_status", i915_context_status, 0},

	{"i915_dump_lrc", i915_dump_lrc, 0},

	{"i915_forcewake_domains", i915_forcewake_domains, 0},

	{"i915_swizzle_info", i915_swizzle_info, 0},

	{"i915_ppgtt_info", i915_ppgtt_info, 0},
@@ -4847,7 +4709,6 @@ static const struct drm_info_list i915_debugfs_list[] = { 
	{"i915_display_info", i915_display_info, 0},

	{"i915_engine_info", i915_engine_info, 0},

	{"i915_shrinker_info", i915_shrinker_info, 0},

	{"i915_semaphore_status", i915_semaphore_status, 0},

	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},

	{"i915_dp_mst_info", i915_dp_mst_info, 0},

	{"i915_wa_registers", i915_wa_registers, 0},