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Commit 3e7a716a authored by Linus Torvalds's avatar Linus Torvalds
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Pull crypto update from Herbert Xu:
 - CTR(AES) optimisation on x86_64 using "by8" AVX.
 - arm64 support to ccp
 - Intel QAT crypto driver
 - Qualcomm crypto engine driver
 - x86-64 assembly optimisation for 3DES
 - CTR(3DES) speed test
 - move FIPS panic from module.c so that it only triggers on crypto
   modules
 - SP800-90A Deterministic Random Bit Generator (drbg).
 - more test vectors for ghash.
 - tweak self tests to catch partial block bugs.
 - misc fixes.

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (94 commits)
  crypto: drbg - fix failure of generating multiple of 2**16 bytes
  crypto: ccp - Do not sign extend input data to CCP
  crypto: testmgr - add missing spaces to drbg error strings
  crypto: atmel-tdes - Switch to managed version of kzalloc
  crypto: atmel-sha - Switch to managed version of kzalloc
  crypto: testmgr - use chunks smaller than algo block size in chunk tests
  crypto: qat - Fixed SKU1 dev issue
  crypto: qat - Use hweight for bit counting
  crypto: qat - Updated print outputs
  crypto: qat - change ae_num to ae_id
  crypto: qat - change slice->regions to slice->region
  crypto: qat - use min_t macro
  crypto: qat - remove unnecessary parentheses
  crypto: qat - remove unneeded header
  crypto: qat - checkpatch blank lines
  crypto: qat - remove unnecessary return codes
  crypto: Resolve shadow warnings
  crypto: ccp - Remove "select OF" from Kconfig
  crypto: caam - fix DECO RSR polling
  crypto: qce - Let 'DEV_QCE' depend on both HAS_DMA and HAS_IOMEM
  ...
parents c2df436b ce5481d0
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+19 −0
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* AMD Cryptographic Coprocessor driver (ccp)

Required properties:
- compatible: Should be "amd,ccp-seattle-v1a"
- reg: Address and length of the register set for the device
- interrupt-parent: Should be the phandle for the interrupt controller
  that services interrupts for this device
- interrupts: Should contain the CCP interrupt

Optional properties:
- dma-coherent: Present if dma operations are coherent

Example:
	ccp@e0100000 {
		compatible = "amd,ccp-seattle-v1a";
		reg = <0 0xe0100000 0 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <0 3 4>;
	};
+25 −0
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Qualcomm crypto engine driver

Required properties:

- compatible  : should be "qcom,crypto-v5.1"
- reg         : specifies base physical address and size of the registers map
- clocks      : phandle to clock-controller plus clock-specifier pair
- clock-names : "iface" clocks register interface
                "bus" clocks data transfer interface
                "core" clocks rest of the crypto block
- dmas        : DMA specifiers for tx and rx dma channels. For more see
                Documentation/devicetree/bindings/dma/dma.txt
- dma-names   : DMA request names should be "rx" and "tx"

Example:
	crypto@fd45a000 {
		compatible = "qcom,crypto-v5.1";
		reg = <0xfd45a000 0x6000>;
		clocks = <&gcc GCC_CE2_AHB_CLK>,
			 <&gcc GCC_CE2_AXI_CLK>,
			 <&gcc GCC_CE2_CLK>;
		clock-names = "iface", "bus", "core";
		dmas = <&cryptobam 2>, <&cryptobam 3>;
		dma-names = "rx", "tx";
	};
+1 −0
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@@ -197,6 +197,7 @@ Code Seq#(hex) Include File Comments
					<mailto:gregkh@linuxfoundation.org>
'a'	all	linux/atm*.h, linux/sonet.h	ATM on linux
					<http://lrcwww.epfl.ch/>
'a'	00-0F	drivers/crypto/qat/qat_common/adf_cfg_common.h	conflict! qat driver
'b'	00-FF				conflict! bit3 vme host bridge
					<mailto:natalia@nikhefk.nikhef.nl>
'c'	all	linux/cm4000_cs.h	conflict!
+6 −0
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@@ -7250,6 +7250,12 @@ M: Robert Jarzmik <robert.jarzmik@free.fr>
L:	rtc-linux@googlegroups.com
S:	Maintained

QAT DRIVER
M:      Tadeusz Struk <tadeusz.struk@intel.com>
L:      qat-linux@intel.com
S:      Supported
F:      drivers/crypto/qat/

QIB DRIVER
M:	Mike Marciniszyn <infinipath@intel.com>
L:	linux-rdma@vger.kernel.org
+2 −1
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@@ -32,7 +32,8 @@
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

	compatible = "fsl,sec-v6.0";
	compatible = "fsl,sec-v6.0", "fsl,sec-v5.0",
		     "fsl,sec-v4.0";
	fsl,sec-era = <6>;
	#address-cells = <1>;
	#size-cells = <1>;
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