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Commit 3cf6fa1e authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Enable SH-X3 hardware synonym avoidance handling. 



This enables support for the hardware synonym avoidance handling on SH-X3
CPUs for the case where dcache aliases are possible. icache handling is
retained, but we flip on broadcasting of the block invalidations due to
the lack of coherency otherwise on SMP.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent d9c94446

arch/sh/mm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ cacheops-$(CONFIG_CPU_SH3) := cache-sh3.o 
cacheops-$(CONFIG_CPU_SH4)		:= cache-sh4.o flush-sh4.o

cacheops-$(CONFIG_CPU_SH5)		:= cache-sh5.o flush-sh4.o

cacheops-$(CONFIG_SH7705_CACHE_32KB)	+= cache-sh7705.o

cacheops-$(CONFIG_CPU_SHX3)		+= cache-shx3.o



obj-y			+= $(cacheops-y)

arch/sh/mm/cache-shx3.c

0 → 100644
+35 −0
Original line number Diff line number Diff line 
/*

 * arch/sh/mm/cache-shx3.c - SH-X3 optimized cache ops

 *

 * Copyright (C) 2010  Paul Mundt

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/io.h>

#include <asm/cache.h>



#define CCR_CACHE_SNM	0x40000		/* Hardware-assisted synonym avoidance */

#define CCR_CACHE_IBE	0x1000000	/* ICBI broadcast */



void __init shx3_cache_init(void)

{

	unsigned int ccr;



	ccr = __raw_readl(CCR);



	if (boot_cpu_data.dcache.n_aliases)

		ccr |= CCR_CACHE_SNM;



#ifdef CONFIG_SMP

	/*

	 * Broadcast I-cache block invalidations by default.

	 */

	ccr |= CCR_CACHE_IBE;

#endif



	writel_uncached(ccr, CCR);

}

arch/sh/mm/cache.c

+7 −0
Original line number Diff line number Diff line
@@ -334,6 +334,13 @@ void __init cpu_cache_init(void) 
		extern void __weak sh4_cache_init(void);



		sh4_cache_init();



		if ((boot_cpu_data.type == CPU_SH7786) ||

		    (boot_cpu_data.type == CPU_SHX3)) {

			extern void __weak shx3_cache_init(void);



			shx3_cache_init();

		}

	}



	if (boot_cpu_data.family == CPU_FAMILY_SH5) {